| CAUSE: | You assigned the specified clock settings to the input or output of the specified ClockLock PLL, HSDI PLL, or LVDS PLL. However, the Quartus II software does not support Clock Setting assignments on PLL inputs or outputs. The Quartus II software automatically creates an appropriate clock for the PLL during compilation. |
| ACTION: | Remove the Clock Setting assignment from the input or output of the PLL. |
See also:
Assigning Clock Settings to a Clock Signal
Deleting Clock Settings
Overview: Using the Timing Analyzer
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