Quartus

Verilog HDL Case Statement warning: implemented Verilog HDL full_case directive at <location> -- differences between design synthesis and simulation may occur

CAUSE: At the specified location in a Verilog Design File (.v), you used the full_case directive in a Case Statement that does not contain all possible state values or a Default Statement. The full_case directive directs the Logic Synthesizer to treat unspecified state values in the Case Statement as don't care values. The Logic Synthesizer implemented the full_case directive; however, in doing so, the Logic Synthesizer may have created synthesized logic for the current design with functionality that differs from the functionality that you simulated for the design.
ACTION: If possible, change the Case Statement so it is "full," that is, all the state values in the Case Statement are specified or the Case Statement contains a Default Statement. You can then remove the full_case directive from the Case Statement.

See also:

full_case language directive
Verilog HDL Language Directives

- PLDWorld -

 
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