Verilog HDL Language Directives

The Quartus^® II software supports the following Verilog HDL language directives, which you can use in a Verilog Design File (.v) to direct the Logic Synthesizer to perform or not perform certain actions when synthesizing a design:

translate_off translate_on	Directs the Logic Synthesizer to ignore portions of the design code that are specific to simulation and not relevant to logic synthesis.
full_case	Directs the Logic Synthesizer to treat unspecified state values in a Verilog Design File Case Statement as don't care values, and therefore to treat the Case Statement as "full".
parallel_case	Directs the Logic Synthesizer to implement parallel logic rather than a priority scheme for all case item expressions in a Verilog Design File Case Statement.
preserve	Directs the Logic Synthesizer to not minimize or remove a particular register when eliminating redundant registers or registers with constant drivers.
maxfan	Directs the Logic Synthesizer to duplicate a register to ensure that the register's fan-out does not exceed the maximum value you specify.
read_comments_as_HDL	Directs the Logic Synthesizer to perform logic synthesis on portions of the design code that are in comments.
keep	The current version of the Quartus II software does not support a `keep` language directive. Instead, you can keep wire and net configurations in a design intact during logic minimization by inserting an `LCELL` primitive into a Verilog Design File for the design.

To use a language directive in a Verilog Design File, you specify the language directive in a comment in the file. The comment can use one of the following formats:

/* <comment> */
// <comment>

In the comment, precede the language directive with the synthesis keyword. You can also precede the language directive with one of the following keywords:

synopsys
pragma
exemplar

For example, you can use the following comment to use the preserve language directive in a Verilog Design File:

 /* synthesis preserve */

For Verilog 2001, you can also use the (* and *) delimiters to use a language directive in a Verilog Design File. For example, you can use the following code to use the preserve language directive:

(* preserve *)

Language directives are also known as "pragmas" or "logic synthesis directives." Verilog HDL language directives are case-sensitive.

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