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A Verilog HDL language directive that directs the Logic Synthesizer to duplicate a register to ensure that the register's fan-out does not exceed the maximum value you specify. You can use this option to reduce the load of critical signals in the design, thereby improving performance.

You can use this language directive only in designs that target APEX^™ 20K, APEX^™ II, ARM^®-based Excalibur^™, Cyclone^™, Stratix^™, or Stratix^™ GX devices.

To use the maxfan language directive, you can specify the maxfan language directive in a comment that is on the same line as the register for which you want the Logic Synthesizer to control fan-out. In the comment, precede the language directive with the synthesis keyword.

For example, in the following code, the comment /* synthesis maxfan 200 */ directs the Logic Synthesizer to duplicate the clkgen register to ensure that the register's fan-out does not exceed the maximum value of 200:

reg clk_gen /* synthesis maxfan 200 */;

For Verilog 2001, you can also use the (* and *) delimiters to use a language directive in a Verilog Design File. For example, you can use the following code to use the maxfan language directive:

(* maxfan *)

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