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A Verilog HDL language directive that directs the Logic Synthesizer to perform logic synthesis on portions of the design code that are in comments. By commenting out code in the design and using this language directive, you can direct the Logic Synthesizer to perform logic synthesis on code that is specific to logic synthesis, while also ensuring that the code does not affect design simulation.

To use the read_comments_as_HDL language directive, you can specify the read_comments_as_HDL language directive with the on keyword in a comment located immediately before the comments you want the Logic Synthesizer to process, and specify the read_comments_as_HDL language directive with the off keyword in a comment located immediately after the comments you want the Logic Synthesizer to process. In the comment, precede the language directive with the synthesis keyword.

For example, in the following code, the Logic Synthesizer performs logic synthesis on the comments // my_rom lpm_rom (.address (address), and // .data (data));. The Logic Synthesizer does not perform logic synthesis on any comments after the comment // synthesis read_comments_as_HDL off (unless the user uses the read_comments_as_HDL language directive again).

// synthesis read_comments_as_HDL on
// // my_rom instantiation
// my_rom lpm_rom 	(.address (address),
//                       .data      (data));
// synthesis read_comments_as_HDL off

When you use the read_comments_as_HDL language directive, the Logic Synthesizer does not perform logic synthesis on comments that contain two or more sets of comment delimiters. In the example above, the Logic Synthesizer does not process the comment // // my_rom instantiation.

For Verilog 2001, you can also use the (* and *) delimiters to use a language directive in a Verilog Design File. For example, you can use the following code to use the read_comments_as_HDL language directive:

(* read_comments_as_HDL *)

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