See Also

A Verilog HDL language directive that directs the Logic Synthesizer to implement parallel logic rather than a priority scheme for all case item expressions in a Verilog Design File (.v) Case Statement. You can use this language directive on Case Statements that do not contain mutually exclusive case item expressions to ensure that overlapping case items can be executed at the same time.

To use the parallel_case language directive, you can specify the parallel_case language directive in a comment following the case, casex, or casez keyword and the case expression. In the comment, precede the language directive with the synthesis keyword.

For example, in the following code, the parallel_case language directive directs the Logic Synthesizer to implement parallel logic on the 3'b1??, 3'b?1?, and 3'b??1 case items expressions:

module parallel_case (sel, a, b, c);
   input [2:0] sel;
   output a, b, c;
   reg a, b, c;

   always @(sel)		
   begin
      {a, b, c} = 3'b0;
      casez (sel)		 // synthesis parallel_case 
         3'b1??: a = 1'b1;
         3'b?1?: b = 1'b1;
         3'b??1: c = 1'b1;
      endcase
   end
endmodule

For Verilog 2001, you can also use the (* and *) delimiters to use a language directive in a Verilog Design File. For example, you can use the following code to use the parallel_case language directive:

(* parallel_case *)

Because the case item expressions are implemented with a priority scheme during design simulation, the functionality you simulate for a design may be different from the functionality the Logic Synthesizer creates for the design using the parallel_case language directive. In the previous example, the Simulator implements a priority scheme for the case item expressions where the bits of the input sel have a high-to-low priority order of sel[2], sel[1], and sel[0], while the Logic Synthesizer implements parallel logic where all the bits of sel have equal priority.

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