See Also

The current version of the Quartus^® II software does not support a keep language directive. Instead, you can keep wire and net configurations in a design intact during logic minimization by inserting an LCELL primitive into a Verilog Design File (.v) for the design. The LCELL primitive always consumes one logic cell, and is not removed from a design during logic synthesis; as a result, the LCELL primitive can prevent the Logic Synthesizer from minimizing or removing wires and nets from the design.

For example, in the following code, the LCELL primitive prevents the Logic Synthesizer from removing the keep1 and keep2 wires:

wire keep1;
wire keep2;
wire ab_or_cd;

assign ab_or_cd = (a & b) | (c & d);
LCELL lcell_keep1(ab_or_cd, keep1);
LCELL lcell_keep2(ab_or_cd, keep2);

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