See Also

Verilog HDL language directives that direct the Logic Synthesizer to ignore portions of the design code that are specific to simulation and not relevant to logic synthesis.

To use the translate_off and translate_on language directives, you can specify the translate_off language directive in a comment located immediately before the code you want the Logic Synthesizer to ignore, and specify the translate_on language directive in a comment located immediately after the code you want the Logic Synthesizer to ignore. In the comment, precede the language directive with the synthesis keyword.

For example, in the following code, the Logic Synthesizer ignores the code #tpd; and performs logic synthesis on any code after the comment // synthesis translate_on (unless the user uses the translate_off and translate_on language directives again):

parameter tpd = 2;  // Generic delays

// synthesis translate_off 
#tpd;
// synthesis translate_on 

For Verilog 2001, you can also use the (* and *) delimiters to use a language directive in a Verilog Design File. For example, you can use the following code to use the translate_off and translate_on language directives:

(* translate_off *)
(* translate_on *)

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