See Also

A Verilog HDL language directive that specifies that the Logic Synthesizer not minimize or remove a particular register. You can use this language directive to preserve a register so you can observe the register during simulation or with the SignalTap^® II Logic Analyzer. You can also use this language directive to create a preliminary version of the current design in which secondary signals are not specified.

You cannot use this language directive for registers that have no fan-out.

To use the preserve language directive, you can specify the preserve language directive in a comment located in the same line as the register you want the Logic Synthesizer to preserve. In the comment, precede the language directive with the synthesis keyword.

For example, in the following code, the comment /* synthesis preserve */ directs the Logic Synthesizer to preserve the reg1 register:

reg reg1 /* synthesis preserve */;

For Verilog 2001, you can also use the (* and *) delimiters to use a language directive in a Verilog Design File. For example, you can use the following code to use the preserve language directive:

(* preserve *)

Back to Top