VHDL Language Directives & Attributes

The Quartus^® II software supports the following VHDL attributes and language directives, which you can use in a VHDL Design File (.vhd) to direct the Logic Synthesizer to perform or not perform certain actions when synthesizing a design:

translate_off translate_on	VHDL language directives that direct the Logic Synthesizer to ignore portions of the design code that are specific to simulation and not relevant to logic synthesis.
preserve	A VHDL attribute that directs the Logic Synthesizer to not minimize or remove a particular register when eliminating redundant registers or registers with constant drivers.
maxfan	A VHDL attribute that directs the Logic Synthesizer to duplicate a register to ensure that the register's fan-out does not exceed the maximum value you specify.
read_comments_as_HDL	A VHDL language directive that directs the Logic Synthesizer to perform logic synthesis on portions of the design code that are in comments.
keep	The current version of the Quartus II software does not support a `keep` language directive. Instead, you can keep wire and net configurations in a design intact during logic minimization by inserting an `LCELL` primitive into a VHDL Design File for the design.

To use an attribute in a VHDL Design File, you must first declare the attribute in an Attribute Declaration. You can then use the attribute by associating the attribute to registers in Attribute Specifications. For example, the following Attribute Declaration declares the maxfan attribute, and the following Attribute Specification associates the maxfan attribute to the clkgen register and specifies a value of 200 for the attribute:

attribute maxfan : integer ;
attribute maxfan of clk_gen : integer is 200;

To use a language directive in a VHDL Design File, you specify the language directive in a comment in the file. The comment can use the following format:

-- <comment>

In the comment, precede the language directive with the synthesis keyword. You can also precede the language directive with one of the following keywords:

synopsys
pragma
exemplar

For example, you can use the following comment to use the translate_off language directive in a VHDL Design File:

-- synthesis translate_off

Language directives are also known as "pragmas" or "logic synthesis directives."

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