A Report window, HTML-Format Report File (.htm), or Text-Format Report File (.rpt) contains some or all of the sections listed below. Sections are listed in the order in which they appear in the window or file.

Sections (Compilation or Simulation Report)

• Legal Notice Section
• Project Settings Folder
  • General Settings Section
• Results for "<name>" Compiler/Simulator Settings Folder
  • Summary Section
  • Messages Section
  • Processing Time Section

Sections (Compilation Report)

• Results for "<name>" Compiler Settings Folder
  • Compiler Settings Section
  • Hierarchy Section
  • Logic Options Section
  • Device Options Section
  • Floorplan View Section
  • Netlist Optimizations Folder
    • Duplicate Logic Elements Section
    • Gate-Level Retiming Section
    • Logic Element Level LUT Resynthesis Section
    • Register Duplication into I/Os Section
  • Synthesis Section Folder
    • Resource Utilization by Entity Section
    • Resource Utilization by Entity - Second Pass
  • Resource Section Folder
    • Resource Usage Summary Section
    • Resource Utilization by Entity Section
    • LogicLock^™ Region Resource Usage Section
    • Input Pins Section
    • Output Pins Section
    • Bidir Pins Section
    • Delay Chain Summary Section
    • All Package Pins Section
    • Control Signals Section
    • Global & Other Fast Signals Section
    • Peripheral Signals Section
    • Carry Chains Section
    • Cascade Chains Section
    • Parallel Expanders Section
    • Embedded Cells Section
    • Non-Global High Fan-Out Signals Section
    • LAB Section
    • Local Routing Interconnect Section
    • MegaLAB^™ Interconnect Section
    • LAB External Interconnect Section
    • MegaLAB Usage Summary Section
    • Row Interconnect Section
    • LAB Column Interconnect Section
    • EAB Column Interconnect
    • ESB Column Interconnect
    • LVDS Section
    • Cliques Section
    • ClockLock^® Section
    • Priority LAB Column Interconnect Section
    • Priority Row Interconnect Section
    • Row Summary Section
    • HSDI Section
    • RAM Summary Section
    • PLL Summary Section
    • PLL Usage Section
    • Differential I/O Receiver Section
    • Differential I/O Transmitter Section
    • Differential I/O Receiver with Dynamic Phase Alignment Section
    • DSP Block Usage Summary Section
    • DSP Block Details Section
    • GXB Receiver Channel Section
    • GXB Transmitter Channel Section
    • Migration Devices Section
    • I/O Bank Usage Section
    • Output Pin Load for Reported TCO Section
    • I/O Standards Section folder
    • I/O Standard Section
    • IOVCC Groups
    • IOGND Groups
    • IOVCC Pins
    • IOGND Pins
    • Dedicated Inputs I/O
    • LAB and Routing Section folder
    • Interconnect Usage Summary Section
    • LAB Logic Elements Section
    • LAB-wide Signals Section
    • LAB Signals Sourced Section
    • LAB Signals Sourced Out Section
    • LAB External Interconnect Section
    • LAB Distinct Inputs Section
    • LAB Macrocells Section
    • Shareable Expanders Section
    • Parallel Expanders Section
    • Logic Cell Interconnection Section
  • Design Assistant Folder
    • Design Assistant Settings Section
    • Design Assistant Results Section
    • Design Assistant Summary Section
    • Design Assistant HardCopy^™ Test Pins Section
  • State Machines Section
  • Equations Section
  • Pin-Out File Section
  • Timing Analyses Folder (for a compilation run without timing assignments or requirements)
    • Timing Settings Section
    • Hold Violations Section
    • fmax (not incl. delays to/from pins) Section
    • Register-to-Register fmax Section
    • tsu (Input Setup Time) Section
    • th (Input Hold Time) Section
    • tco (Clock to Output Delays) Section
    • tpd (Pin-to-Pin Delays) Section
    • RSKM (Receiver Input Skew Margin) Section
    • TCCS (Channel-to-Channel Skew)
  • Timing Analyses Folder (for a compilation run with timing requirements)
    • Timing Settings Section
    • Hold Violations Section
    • tpd Requirements Section
    • tsu Requirements Section
    • th Requirements Section
    • tco Requirements Section
  • Timing Analyses Folder (for a compilation run with complex timing assignments)
    • Timing Settings Section
    • Clock Requirement Section
    • tpd Minimum Requirements Section
    • Hold Violations Section
    • tsu (Input Setup Time) Section
    • th (Input Hold Time) Section
    • tco (Clock to Output Delays) Section
• Results for "<name>" Simulator Settings Folder

Sections (Simulation Report)

• Results for "<name>" Simulator Settings Folder
  • Simulator Settings Section
  • Simulation Waveforms Section
  • Logical Memories Section
• Results for "<name>" Compiler Settings Folder  More Details

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