Design Reuse Manual critique

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Here you will find a selected collection of papers, references and other information, all of which will be of great value to today's designers and managers of complex systems. Each library object includes an opinionated review of its more noteworthy insights so you can tap into its value quickly. And to make your perusal simpler, you will soon be able to search the library quickly and easily.

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Library index.
We've organized the Qualis Library into a few distinct categories. You'll find useful, relevant information on system and ASIC design quickly by selecting a category from the choices below.

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Methodology
Briefs

Brief whitepapers on the latest design methodologies

On the Edge:
Technology Trends

Brief articles on the technology that defines "the edge"

World Class
Design Successes

Articles from people doing the impossible

Day-to-Day
Wisdom

Truly useful design information you can use every day

Technology
Resources

Design resources that help make the impossible, possible

Sanity
Check

Articles that can trigger uncontrollable laughter. Really.



Methodology Briefs

Design Environment Setup and Management

Managing VHDL Models with Makefiles (Here)


Verification and Testing

Online Seminar: Modern Methods for
Verification of System-on-Chip

Online Seminar: A Strategic Process for
System-Level Verification (Here)

The Seven Deadly Sins of Scan-Based Design


Desiging with Reuse in Mind

The Reuse Methodology Manual: A Constructive Critique



On the Edge: Technology Trends

Design for Reuse and IP

Companies Retool for Design Reuse

Engineers Speak Out on Deep-Submicron

Designers Talk about Deep-Submicron Design

DSM Increases the Need for Experienced Design Teams


Hardware/Software Co-Design

Differentiating between Co-Design and Co-Debug


Behavioral Synthesis

Behavioral Synthesis Methods for HDL-based
Specification and Validation (Here)



World Class Design Successes

Large System Verification

Verifying the PA-8000's FPU

Verifying a Million Gate Processor



Day-to-Day Wisdom

Design Practices

Design Rules for Stable, Reliable Synchronous Systems (Here)

Matching the Design Size to an ASIC or FPGA (Here)

Why Use 2 Registers to Synchronize an
Asynchronous Input? (Here)


Synthesis

Working with Behavioral Compiler: Some Helpful Tips (Here)

9 Area Reduction Tricks Using Synopsys DC (Here)

Steve Golson's Favorite dc_shell Tricks (Here)


Low Power Design

Low Power Design Issues, Tools and Methodologies (Here)



Technology Resources

Productivity Enhancement Tools




VMK/LMK: A Real VHDL Makefile Generator

dc_perl: Extending Synopsys' dc_shell Commands

Push-button Synthesis: Using dc_perl to do_the_right_thing

vpp: A Powerful Verilog Preprocessor

LOGSCAN: A Configurable Error Management Tool

Emacs editor modes for Verilog, VHDL and dc-shell (Here)


Information Resources

Searchable Archives of HDL and EDA Newsgroups

Verilog and VHDL Quick Reference Cards (Here)



Sanity Check

The Twisted Humor of John Cooley

Murder, He Wrote


So Funny, it's Scary

The Dilbert Zone


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