Verilog HDL is one of popular hardware description languages. There are coding examples written by VerilogHDL. They are available to use on Cadence Design Framework II in Tokyo Institute of Technology. They are already checked their performance by Logic Simulator "Verilog XL". However there may be several buggs which I cannot detect. Please send e-mail to "tootsuka@de.tokyo-ct.ac.jp" if you find buggs.
| Module Name | Abstract. |
|---|---|
| ckgen | clock generator |
| d-ff | d flip flop ( 74LS74 ) |
| ls138 | 3 to 8 demultiplexer |
| ls139 | dual 2 to 4 demultiplexer |
| ls151 | 8 to 1 data selector |
| ls153 | dual 4 to 1 data selector |
| ls163 | syncronous 4 bit counter |
| ls169 | syncronous up/down counter |
| ls175 | quad d-ffs |
| ls181 | arithmatic logic unit |
| ls194 | 4 bits shift register |
| ls257 | quadruple 2 line to 1 line data selector/multiplexers |
| ls374 | octal 3 state d-ffs |
| ls377 | 8 bit d-ffs |
| ls540 | octal 3 state buffer ( inverted ) |
| ls541 | octal 3 state buffer |
| ls157 | quad 2 to 1 data selector |
| rsff | set-reset flip flop |
| m6116 | 16kB SRAM |
| i2764 | 64kB ROM |
| Module Name | Abstract. |
|---|---|
| cg | clock generator |
| pc | program counter (4 bit) |
| gr4 | general register (4 bit) |
| alu | alithmatic logic unit (4 bit) |
| multifier | multifier (integer 8bit) |