Frequently Asked Questions

1. Led Tutorial.

2. How to run AutoCells ?

3. How to do Design Rule Checking ?

4. How do I extract Hspice/Lsim netlist using maskcheck ?

5. How do I do netcheck ?

6. How do I run Lmask ?

7. Where are the technology files ?

8. How do I get Mosis Submission ?

9. How do I run the padframe program ?

10. How do I simulate a full chip using Lsim ?

11. How do I scale from one technology to another ?

12. What DRC errors are present in the cells? ?

13. How do I get my layout into the GDSII format required by MOSIS ?

14. MicroRoute Tutorial

15. Lsim Adept mode technology files are now fixed.


16. Lsim Tips.


Sample Layouts .

3. How to do Design Rule Checking

To do design rule checking from inside Led enter upper case L. This does not check for all the design rules. For checking out all the rules run the mask check program as follows:

mcDrGdt Lfile
where Lfile is the layout file. The output file with the errors is stored in the DesignName_dre.txt file. The -a option can be made use of while running the program. This option requests all intermediate files to be left. Click here for a detailed review on the Design Rules

4. How do I extract a netlist using maskcheck ?

The netlist extraction scripts are in the following directory

$MSU_SCMOS/mentor_scs/tech_files/rel/ckmt/bin
The program mcExtGdt is used for extracting the netlist from the layout. To extract the netlist for Hspice do
mcExtGdt hspice Lfile
where Lfile is the name of the Layout file. The output netlist is stored in the DesignName.spice file. To extract the netlist for Lsim do
mcExtGdt lsim Lfile
The output netlist is stored in the DesignName.N file There are certain options available which can be made use of while running the program. They are listed below
mcExtGdt [-e equivFileName] [-a] netlistType LFile ...
netlistType -- lsim, hspice, or hspice_para (hspice_para
includes parasistic elements but takes much longer)
LFile ... -- List of L files that need to be extracted. The
name of the cell to be checked in each L file is assumed to be
the file's base name.
-e equivFileName -- Pathname specifying a file with signal names
that are equivalent. If not specified, a default is used.
This is needed to prevent the detection of false shorts.
-a -- Requests that all intermediate files be left. This can be
helpful for manually changing the run parameters.

5. How do I do netcheck ?

Netcheck is a tool which compares the connectivtiy of the layout with it's schematic. To run the netcheck program which is in the $MSU_SCMOS/mentor_scs/tech_files/rel/ckmt/bin directory do

ncGdt Lfile Sfile
where Lfile is the Layout file name and Sfile is the Schematic file name If the connectivity in both files are not the same then the errors are stored in the DesignName.ncErr file. Before running the netcheck make sure that:
All the signal names and terminal names are added as VIEWNAME and not as TEXT. If this is not done the netcheck program will give warnings.
The number of transistors in the schematic and the layout are equal. There are certain options available which can be made use of while running the program. They are listed below
ncGdt [-aps] LFile ... SFile ...
LFile ... SFile ... -- This should be a list of layouts
(L files) followed by an equal number of schematics (S files).
The layouts and schematics will be matched up in the order
they are given. The name of the cell to be checked in each
L file is assumed to be the file's base name.
-a -- Requests that all intermediate files be left. This can be
helpful for manually changing the run parameters.
-p -- Requests that the transistor parameters (width and length)
be compared.
-s -- Requests that transistors in series not be considered
interchangeable.

6. How do I run Lmask ?

Lmask is a tool provided by Mentor Graphics which is helpful to fill notches and gaps which are created while designing the layout. This tool is very useful for especially very large designs where filling the notches and the gaps prove to be very tedious. It is important to fill the notches and gaps inorder to prevent mask check errors. To run Lmask do
Lmask -t scn12hp -l $MSU_SCMOS/mentor_scs/tech_files/rel/gdt Lfile -notch -gap -nonets -o Outfile
-Lfile is the name of the layout file
-notch -- Requests that all notches be filled.
-gap -- Requests that all gaps be filled.
-nonets -- Disables all net checking.
-o -- Requests the output be stored in the file Outfile.
The polygons and rectangles representing the gaps and notches are stored in the Outfile. The cells in this file are all with respect to the origin of the original layout. Therefore these cells have to be added to the original layout, by editing the layout file, i.e. instances are added to the top level cell at the origin.
Lmask checks for shorts when filling gaps. If there are shorts then those results are stored in the Lscan.L file. These shorts are actually design rule errors, therefore before running Lmask make sure to run the rule check.
Lmask considers the wide truncated ends of diffusion wires of opposite sides of the same transistor as a short. Therefore these errors can be prevented from appearing in the Lscan.L file by using the -nonets option.

7. Where are the technology files ?

All Technology files are in the following directory:
$MSU_SCMOS/mentor_scs/tech_files/rel/gdt

9. How do I run the padframe program ?

There is a padframe program in the $MSU_SCMOS/mentor_scs/tools directory. This program is useful to create the full chip layout (with the pads) once the core layout has been designed. All MSU pad cells are in the directory $MSU_SCMOS/mentor_scs/pad_lib.

The padframe program uses several of Mentor Graphics tools. The procedure for running the padframe generator is as follows:

I. Set environment variable and path in your .cshrc file

setenv PadFrameGen /projects/mpl/msu_scmos/release/mentor_scs/tools/padframe_gen/src
set tpath = (/projects/mpl/msu_scmos/release/mentor_scs/tools/padframe_gen/src)

II. Create the hierarchic schematic for the design.

1. Your top level schematic must have 8 padframe blocks surrounding the core: left block, top left block, top block, top right block, right block, bottom right block, bottom block, and bottom left block in which top left block, top right block, bottom left block, and bottom right block can be corner pad in release library.
2. The cell name of a schematic must be the same as its corresponding layout.
3. Terminal names in a schematic cell must be same as those in a layout cell.
4. The orientation of an instance in the schematic cell of a pad must be the same as in its corresponding layout cell.
5. The library cells should be hierarchial as shown in the pad_lib directory.

III. Run AutoCells to create your design core layout.

IV. In your working directory, You should have the following five files before running padframe generator. Don't change any file name.

MicroRoute.par -- example provided in padframe directory.
assemble_chip.m -- example provided in padframe directory.
layout_inc -- the user created layout cells include file
schematic_inc -- the user created include file for the design schmatic
pad_location.par -- pad location and power parameter created by user.

V. Enter the following command on the command line

run_padframe technology_name design_name

A more detailed tutorial can be found here .

10. How do I simulate a full chip using Lsim ?

After the padframes have been created, the whole chip can be simulated using Lsim. Inorder to simulate we require the netlist which can be extracted from the layout using the script mcExtGdt in the /tech_files/rel/ckmt/bin directory. Run the script as follows:
mcExtGdt lsim chip.L
This will generate the file chip.N which is the netlist file. To run Lsim do:
Lsim -t scn12hp -l $MSU_SCMOS/mentor_scs/tech_files/rel/gdt chip.N &
Inoder to apply inputs an input file called chip.i has to be created. An example of the chip.i file is present in the $MSU_SCMOS/tools/padframe/tutor/scn12hp directory.

11. How do I scale from one technology to another ?

To scale a layout from one technology to another do:
SCALE.go old_lib old_tech old_Lfile new_lib new_tech new_Lfile paramter_file
The library (old_lib/new_lib) specifies the whole path of the technology file. The technology (old_tech/new_tech) is the name of the technology. old_Lfile and new_Lfile refer to the old and new layout file names.The Parameter_files are present in the respective technology directories. For example to scale from scn08hp to scn12hp do:
SCALE.go $MSU_SCMOS/mentor_scs/tech_files/rel/gdt scn12hp old.L
$MSU_SCMOS/mentor_scs/tech_files/rel/gdt scn08hp new.L
$MSU_SCMOS/mentor_scs/tech_files/rel/gdt/scn12hp.dir/1.2_to_0.8

12. What DRC errors are present in the cells?

The only DRC error present in the cell layouts is rule 8.5 - Via spacing to poly or active edge. We have maintained only a 1 lambda spacing in some places instead of the required 2 lambda, this has not proven to be a problem in fabricated designs. This error WILL be reported via the 'maskcheck' DRC. There are several reported DRC errors in the 1.2u pads which arises from the input protection scheme - again, these have not proven to be a problem in fabricated designs.

13. How do I get my layout into the GDSII format required by MOSIS ?

To convert a layout to GDSII format: 
Lc -t $tech -l $tech_dir -gds2merge -o chip.gds chip.L
Where 'chip.L' is the input file in 'L' format and 'chip.gds' will be the output in GDSII format. '$tech' is the technology being used and '$tech_dir' is the technology directory. The 'Lc' program is the L language compiler in the Mentor/SCS toolset. The GDSII layer numbers specified by Mosis are found in the 'LtoGDSII' file in the technology directory.

15.Lsim Adept mode technology files are now fixed.

Thanks to Richard Auletta, University of Colorado at Denver, for pointing out some problems with the adept mode tables. These are now fixed (LSIM adept mode files are included in the 'tech.tar.Z' file available on the download site).

16.Lsim Tips.

Use the command: 


 mcExtGdt lsim  file.L
file to extract a Lsim netlist file (file.N). CHECK this file; you may need to change the types of the 'vdd' and 'gnd' terminals listed at the top of cell definition to 'VDD' and 'GND' (they maybe extracted as 'INOUT' types). If you do not do this; the your simulation will not work.

To run Lsim do: 

 % Lsim -t tech_name -l tech_directory_name file.N

On startup, Lsim will load a file called 'file.i' if one is present; this should contain simulation commands. This file, reg.N , is the Lsim netlist for an example register file; this file reg.i is the command file to simulate it.

Typing "help" in Lsim will list all LSIM commands; typing "help command" will display the help string for that command.

One useful feature in LSIM is to bring up the debugging window (choose from menu when you right click in the LSIM waveform window), then use the 'traverse' command to traverse the netlist connectivity.

Useful commands: 


 'file command_file' - read commands from file
 'reset' - reset to time zero