Instantiating LPM in Verilog

 

To promote LPM usage in Verilog design community. This section describes the syntax for instantiating LPM in Verilog design file.

Module Declaration

To instantiate component in Verilog design file, the module has to be declared. The declaration of LPM modules is defined in the LPM declaration file . In declaring the LPM module, the module should be "fully described". Which includes all the optional ports, parameters. Once defined, any number of these "fully described modules" can be instantiated within the Verilog design. For example, LPM_MULT is declared as follows:

module lpm_mult ( result, dataa, datab, sum, clock, aclr ) ;
   parameter lpm_type       = "lpm_mult" ;
   parameter lpm_widtha     = 1 ;
   parameter lpm_widthb     = 1 ;
   parameter lpm_widths     = 1 ;
   parameter lpm_widthp     = 1 ;
   parameter lpm_pipeline    = 0 ;
   parameter lpm_representation     = "UNSIGNED" ;

   input  clock ;
   input  aclr ;
   input  [lpm_widtha-1:0] dataa ;
   input  [lpm_widthb-1:0] datab ;
   input  [lpm_widths-1:0] sum ;
   output [lpm_widthp-1:0] result;

    [module body] . . .

endmodule;

  

Module Instantiation

  1. Port
  2. All the used port connections are defined in port map construct of Verilog. The unused optional ports were left out from the port map and its' default value from the component declaration will be used. For example, the u1 instance in this example only use aset optional port of LPM_FF so other unused optional ports were left our from the port map statement.

       LPM_FF u1 (.data(result), .q(last), .clock(clock),.aset(clear));
    
    
  3. Property
  4. All the used LPM properties values are defined in generic map construct of Verilog. The unused optional properties were left out and its' default value from the component declaration will be used. For example, the u1 instance in this example is an 4-but DFF with no synchronous set value (ie. LPM_SVALUE) so the LPM_SVALUE is left out from the generic map statement.

       LPM_FF u1 . . .
          defparam u1.lpm_width = 4;
          defparam u1.lpm_avalue = 1
    
    
  5. Example
  6. The schematic example is shown in the following figure.


    
    
    // Description: LPM instantiation
    //
    `include "/lpm_comp.v"
    
    module fibex (clock, clear, result);
      input clear;
      input clock;
      inout [3:0] result;
      wire [3:0] last;
      wire [3:0] present;
    
      LPM_FF u1 (.data(result), .q(last), .clock(clock), .aset(clear));
          defparam u1.lpm_width = 4;
          defparam u1.lpm_avalue = 1;
    
      LPM_FF u2 (.data(last), .q(present), .clock(clock), .aset(clear));
          defparam u2.lpm_width = 4;
          defparam u2.lpm_avalue = 1;
    
      LPM_ADD_SUB u3 (.dataa(present), .datab(last), .result(result));
          defparam u3.lpm_width = 4;
    
    endmodule
    
       
    Schematic description
    Verilog description

LPM Verilog Declaration file


The following LPM verilog file only contains the module declaration that included the pins and properties of LPM modules. Due the limited support of two dimensional array for non-registered functions, LPM_AND, LPM_OR, LPM_XOR and LPM_MUX modules that hav e two dimensional ports are excluded from this declaration file.

 module lpm_add_sub ( result, cout, overflow, add_sub, cin, dataa, datab, clock, aclr );

   parameter lpm_type = "lpm_add_sub" ;
   parameter lpm_width = 1;
   parameter lpm_pipeline = 0 ;
   parameter lpm_representation    = "signed" ;
   parameter lpm_direction  = "add ;
   parameter lpm_hint = "unused";

   input  [lpm_width-1:0] dataa, datab ;
   input  add_sub, cin ;
   input  clock ;
   input  aclr ;
   output [lpm_width-1:0] result ;
   output cout, overflow ;

 endmodule // lpm_add_sub


 module lpm_compare ( alb, aeb, agb, aleb, aneb, ageb, dataa, datab, clock, aclr);

   parameter lpm_type = "lpm_compare" ;
   parameter lpm_width = 1;
   parameter lpm_pipeline = 0 ;
   parameter lpm_representation = "unsigned" ;
   parameter lpm_hint = "unused";

   input  [lpm_width-1:0] dataa, datab ;
   input  clock ;
   input  aclr ;
   output alb, aeb, agb, aleb, aneb, ageb ;

 endmodule // lpm_compare


 module lpm_constant ( result );

   parameter lpm_type = "lpm_constant" ;
   parameter lpm_width = 1;
   parameter lpm_cvalue = "unused";
   parameter lpm_strength = "unused";

   output [lpm_width-1:0] result ;

 endmodule // lpm_constant


 module lpm_counter ( q, eq, data, clock, clk_en, cnt_en, updown,
         aset, aclr, aload, sset, sclr, sload);

   parameter lpm_type     = "lpm_counter" ;
   parameter lpm_width    = 1;
   parameter lpm_modulus  = "unused" ;
   parameter lpm_avalue   = "unused" ;
   parameter lpm_svalue   = "unused" ;
   parameter lpm_pvalue = "unused";
   parameter lpm_direction  = "unused" ;
   parameter lpm_hint = "unused";

   output [lpm_width-1:0] q ;
   output eq ;
   input  [lpm_width-1:0] data ;
   input  clock, clk_en, cnt_en, updown ;
   input  aset, aclr, aload ;
   input  sset, sclr, sload ;

 endmodule // lpm_counter


 module lpm_decode ( eq, data, enable, clock, aclr);

   parameter lpm_type     = "lpm_decode" ;
   parameter lpm_width    = 1 ;
   parameter lpm_decodes  = 1 << lpm_width ;
   parameter lpm_pipeline = 0 ;

   input  [lpm_width-1:0] data ;
   input  enable ;
   input  clock ;
   input  aclr ;
   output [lpm_decodes-1:0] eq ;

 endmodule // lpm_decode


 module lpm_latch ( q, data, gate, aset, aclr);

   parameter lpm_type = "lpm_latch" ;
   parameter lpm_width = 1 ;
   parameter lpm_avalue = "unused" ;
   parameter lpm_pvalue = "unused";

   input  [lpm_width-1:0] data ;
   input  gate, aset, aclr ;
   output [lpm_width-1:0] q ;

 endmodule // lpm_latch


 module lpm_ram_dq ( q, data, inclock, outclock, we, address);

   parameter lpm_type = "lpm_ram_dq" ;
   parameter lpm_width  = 1 ;
   parameter lpm_widthad = 1 ;
   parameter lpm_numwords = "unused" ;
   parameter lpm_file       = "unused" ;
   parameter lpm_indata   = "registered" ;
   parameter lpm_outdata  = "registered" ;
   parameter lpm_address_control  = "registered" ;

   input  [lpm_width-1:0] data ;
   input  [lpm_widthad-1:0] address ;
   input  inclock, outclock, we ;
   output [lpm_width-1:0] q;

 endmodule // lpm_ram_dq


 module lpm_ram_io ( dio, inclock, outclock, we, memenab, outenab, address);

   parameter lpm_type = "lpm_ram_io" ;
   parameter lpm_width  = 1 ;
   parameter lpm_widthad = 1 ;
   parameter lpm_numwords = "unused" ;
   parameter lpm_file       = "unused" ;
   parameter lpm_indata     = "registered" ;
   parameter lpm_outdata    = "registered" ;
   parameter lpm_address_control = "registered" ;

   input  [lpm_widthad-1:0] address ;
   input  inclock, outclock, we ;
   input  memenab ;
   input  outenab ;
   inout  [lpm_width-1:0] dio ;

 endmodule // lpm_ram_io


 module lpm_rom ( q, inclock, outclock, memenab, address);

   parameter lpm_type = "lpm_rom" ;
   parameter lpm_width    = 1 ;
   parameter lpm_widthad = 1 ;
   parameter lpm_numwords = "unused" ;
   parameter lpm_file       = "rom.hex" ;
   parameter lpm_outdata    = "registered" ;
   parameter lpm_address_control = "registered" ;


   input  [lpm_widthad-1:0] address ;
   input  inclock, outclock ;
   input  memenab ;
   output [lpm_width-1:0] q;

 endmodule // lpm_rom


 module lpm_bustri ( result, tridata, data, enabledt, enabletr);

   parameter lpm_type = "lpm_bustri" ;
   parameter lpm_width  = 1 ;
   input  [lpm_width-1:0] data ;
   input  enabletr ;
   input  enabledt ;
   output [lpm_width-1:0] result;
   inout  [lpm_width-1:0] tridata ;

 endmodule // lpm_bustri


 module lpm_inv ( result, data );

   parameter lpm_type = "lpm_inv" ;
   parameter lpm_width = 1 ;

   input  [lpm_width-1:0] data ;
   output [lpm_width-1:0] result ;

 endmodule // lpm_inv


 module lpm_clshift ( result, overflow, underflow, data,
         direction, distance);

   parameter lpm_type        = "lpm_clshift" ;
   parameter lpm_width       = 2 ;
   parameter lpm_widthdist   = 1 ;
   parameter lpm_shifttype   = "logical" ;

   input  [lpm_width-1:0] data ;
   input  [lpm_widthdist-1:0] distance ;
   input  direction ;
   output [lpm_width-1:0] result;
   output overflow ;
   output underflow;

 endmodule // lpm_clshift


 module lpm_mult ( result, dataa, datab, sum, clock, aclr );

   parameter lpm_type       = "lpm_mult" ;
   parameter lpm_widtha     = 1 ;
   parameter lpm_widthb     = 1 ;
   parameter lpm_widths     = 1 ;
   parameter lpm_widthp     = 1 ;
   parameter lpm_pipeline       = 0 ;
   parameter lpm_representation    = "unsigned" ;

   input  clock ;
   input  aclr ;
   input  [lpm_widtha-1:0] dataa ;
   input  [lpm_widthb-1:0] datab ;
   input  [lpm_widths-1:0] sum ;
   output [lpm_widthp-1:0] result;

 endmodule // lpm_mult


 module lpm_ff ( q, data, clock, enable, aclr, aset,
         sclr, sset, aload, sload);

   parameter lpm_type = "lpm_ff" ;
   parameter lpm_fftype = "dff" ;
   parameter lpm_width  = 1 ;
   parameter lpm_avalue = "unused" ;
   parameter lpm_svalue = "unused" ;

   input  [lpm_width-1:0] data ;
   input  clock, enable ;
   input  aclr, aset ;
   input  sclr, sset ;
   input  aload, sload  ;
   output [lpm_width-1:0] q;

 endmodule // lpm_ff


 module lpm_shiftreg ( q, shiftout, data, clock, enable,
         aclr, aset, sclr, sset, shiftin, load);

   parameter lpm_type = "lpm_shiftreg" ;
   parameter lpm_width  = 1 ;
   parameter lpm_avalue = "unused" ;
   parameter lpm_svalue = "unused" ;
   parameter lpm_direction = "left" ;

   input  [lpm_width-1:0] data ;
   input  clock, enable ;
   input  aclr, aset ;
   input  sclr, sset ;
   input  shiftin, load ;
   output [lpm_width-1:0] q;
   output shiftout ;

 endmodule // lpm_shiftreg


 module lpm_abs ( result, overflow, data );

   parameter lpm_type = "lpm_abs" ;
   parameter lpm_width = 1;

   input  [lpm_width-1:0] data ;
   output [lpm_width-1:0] result ;
   output overflow ;

 endmodule // lpm_abs


 module lpm_inpad ( result, pad );

   parameter lpm_type = "lpm_inpad" ;
   parameter lpm_width = 1;

   input  [lpm_width-1:0] pad ;
   output [lpm_width-1:0] result ;

 endmodule // lpm_inpad


 module lpm_outpad ( pad, data );

   parameter lpm_type = "lpm_outpad" ;
   parameter lpm_width = 1;

   input  [lpm_width-1:0] data ;
   output [lpm_width-1:0] pad ;

 endmodule // lpm_outpad


 module lpm_bipad ( pad, enable, data, result );

   parameter lpm_type = "lpm_bipad" ;
   parameter lpm_width = 1;

   input enable ;
   input [lpm_width-1:0] data ;
   input [lpm_width-1:0] result ;
   inout [lpm_width-1:0] pad ;

 endmodule // lpm_bipad


 module lpm_ttable (result, data );

   parameter lpm_type = "lpm_ttable" ;
   parameter lpm_widthin  = 1;
   parameter lpm_widthout = 1;
   parameter lpm_file     = "table.txt" ;
   parameter lpm_turthtype = "fd" ;

   input  [lpm_widthin-1:0] data ;
   output [lpm_widthout-1:0] result ;

 endmodule // lpm_ttable


 module lpm_fsm (result, state, clock, aset, data );

   parameter lpm_type = "lpm_fsm" ;
   parameter lpm_widthin  = 1;
   parameter lpm_widthout = 1;
   parameter lpm_widths   = 1;
   parameter lpm_file     = "fsm.txt" ;
   parameter lpm_avalue = "unused" ;
   parameter lpm_pvalue = "unused";
   parameter lpm_turthtype = "fd" ;

   input  clock ;
   input  aset ;
   input  [lpm_widthin-1:0] data ;
   output [lpm_widths-1:0] state ;
   output [lpm_widthout-1:0] result ;

 endmodule // lpm_fsm

  

 

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