entity
sadc is -- simple analog to digital converter
generic
(niveau: real:= 2.5); -- threshold
port
(terminal at: electrical; -- analog
input
signal ds: out bit); -- digital output
end
sadc;
architecture
simple of sadc is
quantity
vq across at; - - across quantity to ground
begin
ds <= `1' when
vq'above(level) -- vq > level
else `0'; -- vq <level
end
simple;
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entity
sdac is
generic
(vdd: real: = 5.0);
-- vdd constant for analog output port
(signal ds: in
bit; -- logic input
terminal at: electrical); -- analog output
end
sdac;
architecture
simple of sdac is
quantity
vq across at; - - branch quantity to ground
begin
if
ds ='0' use
vq==0.0; -- low output
else
vq==vdd; -- high output
end
use;
break on
ds; - - prevision of discontinuity
end
simple;
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