Lesson eight: Input and Output primitives

8 VHDL program input/output functions

prepared by P. Bakowski

Introduction

In VHDL like in most programming languages there are functions to display text on the screen and to read the user data through the keyboard. Even though your simulator allows to monitor the value of signals and variables in your design, it is also possible to output required information during simulation in order to generate simulation reports. In VHDL this feature is provided through the use of a standard library called textiothat comes with every VHDL simulator.

Contents: screen output, files, simulation report, exercises

Screen output

The description which requires the input/output operations needs to contain:

use textio.all;

immediately before every architecture that uses input and output.

Text is read and written by using textio functions (read and write) and a variable of the type line. Since variables are used for textio, input and output is must be done in processes. The output information is first placed in text form into the variable of type line and then sent to outpu via an additional function called writeline. This is shown in the following example.

use textio.all;
architecture simple of check_overflow is
begin
process (x)
constant maxval: integer:= 800;
variable sor: line;
variable comp : integer:=0;
begin
if (x='1' and x'last_value='0') then
end if;
end process;
end simple;

Comments:
The write function is used to append text information at the end of a linevariable which is empty when the simulator is initialized. The function takes two arguments, the first is the name of the line to append to, and the second is the information to be appended. In the example, sor is set to "overflow :", and then the current value of compis converted to text and added to the end of line.

The writeline function outputs the current value of a line to the screen, and empties the line for re-use. The first argument of the writeline function just indicates that the text should be output to the screen. Given that the maxval is initialized to 100, the message sent to the screan is:

overflow : 800

The write statement can also be used to append constant, variable and signal values of the types bit, bit_vector, time, integer, and real.

Input/output files

File declaration can be used to define a file type which indicates the data type stored in the file.

type logic_values is file of character

This file type can be used to declare input and output files of this type. The following declaration specifies an input file containing ASCII characters.

file logic_values_input : logic_values is in "input.dat"

read function takes a file name and a type of data as its arguments. It reads the next data in the file and places it in its data argument.The arguments of writefunction are similar: the name of file and the data to be written in the file.There is also a function called endfilewhich takes the name of the file as argument and returns true if a subsequent read cannot be done from the file.

The following procedure uses an input file to read a string of characters and assigns them to a bit type.

-- type logic_values visible in procedure
procedure assign_bit(signal res: out bit; file_name: in string) is
variable car: character;
file input_file: logic_values is in file_name;
-- the reading is initialized and starts from the beginning of the file !
begin
end assign_bit;

Remark:

The problem with the above procedure is that each time it is executed the lecture of the file starts from the beginning. The re-use of the same procedure several times without the reading initialization requires the file declaration to be placed outside the procedure. This can take place in a process statement or in the statement part of an architecture.

Simulation report - an example

The following example illustrates how to generate a simulation report .

architecture sim_report of two_phases is

signal ph1: bit :='1';

signal ph2: bit :='0';

begin

phase_one: ph1 <= not ph1 after 400 ns;

phase_two:process

begin

wait until ph1 ='0';

wait for 10 ns

ph2 <= '1';

wait for 320 ns

ph2 <= '0';

end process phase_two;

report_p: process (ph1,ph2)
file sortie: text is out "phases.rep";
variable fill: string (1 to 3):=" ..";
variable tampon: line;
begin

write(tampon,now,right,8,ns);

-- now represents the actual number of nanoseconds in the simulation run

if ph1'event then

write(tampon,ph1,right,3);

write(tampon,fill,left,0)

else

write(tampon,ill,left,0);

write(tampon,ph2,right,3);

end if;

writeline(sortie,tampon) -- writing the line in file "phases.rep";

end process report_p;

end sim_report;

see the content of io_utils package

8

VHDL program input/output functions

Introduction

Screen output

Input/output files

Simulation report - an example

Exercises