functions, procedures, packages and libraries
prepared by P. Bakowski
This chapter introduces the programming constructs called subprograms
VHDL provides basic functional blocks in the form of programming modules
(sub-programs) called procedures
and functions [syntax].
The modules called packages are used to collect declarations of types,
subtypes, functions and procedures into modular units that can be used
in several designs.
In general, the declaration a sub-program can be
done in a package, an entity, an architecture, a process, a procedure or
a function. For functions, the declaration also specifies the type of the
result returned when the function is called.
In this chapter we consider only constant and variable
parameters of subprograms, although signals can also be used .
declaration , function declaration, subprogram
call, subprogram bodies, overloading,
packages, libraries, exercises
Procedures and functions are essential functional
modules provided to describe the algorithms. The algorithms having multiple
results are described as procedures; the algorithms having only one result
are usually described with functions.
Below a simple example of a procedure with no parameters:
This simply defines alarm
as a procedure with no parameters, whose statement body
will be given subsequently in the VHDL program.
A procedure call to alarm
The following is a declaration of a procedure with two parameters:
When the procedure is called, the actual parameter associated with compteur
must itself be a variable.
The operation mode
is in , which means
that init can be read but
Other possible modes
for procedure parameters are:
The default mode is specified of a parameter is in.
If no class is specified (variable,
constant,..) , parameters
of mode in are interpreted as being
of class constant
and parameters of mode out
and inout are interpreted
as being of class variable.
A function is a subprogram which returns one value. Formal parameters
mode must be in , and this is assumed
if not explicitly specified. Default class is assumed to be constant
Note that the value returned by the body of this function must be a
As in any programming language the declared items presented after
the subprogram header are to be used locally within the subprogram body.
The names of these items are visible only inside locally declared
subprograms. When the subprogram is called, the statements in the body
are executed until either the last statement in the program order is encountered,
or a return statement is executed.
The return statement used
within a function carries a return value. This value may be
ready in a variable or it can be evaluated by an expression related to
Note taht the return statement
used within a procedure has no return value.
A call to a subprogram includes a list of actual parameters to be mapped
onto the formal parameters. Two kinds of mapping are possible:
This association list can be position based; it
lists the actual parameters in the same order as the formal parameters.
A subprogram call with named association explicitly
gives the formal parameter name to be associated with each actual parameter
; the parameters can be in any order.
A given subprogram designator (name) can be used in several subprogram
specifications, provided the number or base types of parameters differs.
The subprogram name is then said to be overloaded.
When a subprogram call is made using an overloaded name, the choice of
one of the overloaded specifications depends on the number of actual parameters
their base types , their order and the corresponding formal parameter names.
This means that the selection of the overloaded subprogram is related not
only to the name of the subprogram but also to its parameters.
The following are two specifications of a function called compare;
depending on the parameters used with the name compare
we can select the first or the second version of this function.
It is important that the operator symbols (+,
-, *, & , ...) may be used as names of the functions.
It allows a variety of functions to be defined for these operators. For
example, the addition operator (+)
is often overloaded in order to perform the addition of bit_vector
Note: The "standard" addition
operator (+) is defined originally
to be used only with integers.
A package is a collection of logically related
declarations. They typically are used to contain sets of
type subtypes, constants declarations, global signal
declarations, and global variables (VHDL'93).
The packages may contain component declarations, attribute declarations
and specifications and subprograms. The subprograms declared in packages
provide information hiding; they can be called from outside the package
but the body of the subprograms remains hidden and protected from users.
Normally a package is defined in two parts:
The body part may be omitted if there are
no subprogram implementations or deferred constants.
In the example above, the bodies of the two functions address2int
are not specified , so a package body is needed.
Note the deferred constant cdiff
is initialized in the package body; its value may be changed by re-analyzing
only the package body.
The package body can be written as:
Note that the subtype declarations are not repeated, they are visible
from the package declarations block.
Items declared within a package become accessible by direct selection:
If all of the declared names in a package are to be used in this
way, you can indicate it through special suffix all
, for example:
There are two predefined packages provided with VHDL:
All VHDL compilers
store the compiled designs in design libraries. The standard
package is already compiled into std library and used implicitly
by VHDL compiler. Other VHDL files must be explicitly compiled into
design libraries before the use by simulator.
Library named work is used when no explicit user designed
library is provided.
For comprehensive designs the compiled vhdl modules should be placed
in design libraries other than work. The library name should
reflect the nature of the compiled components (e.g. CMOS_logic).
One of the well known libraries is IEEE standard
logic library. If the compiled vhdl module requires standard logic
, IEEE library must be included into the compilation process.
The synthesis tools use standard numeric packages. These numeric packages
contain the functions which allow to apply the numeric operators to bit
vectors. Depending on the use of simple bit vectors and standard logic
vectors two numeric packages are provided: