9
Standard logic and numeric packages

prepared by P. Bakowski


Contents: std_logic_1164, logic system, resolution function (resolved), numeric packages


The development of complex models should be based on standard packages allowing the use of coherent data types and operators as well as the development of synthetisable descriptions.

The basic data types such as bit or bit_vector do not allow to cope with different meta-logic values required to represent different kinds of signals. A minimal logic to represent all operational aspects of hardware requires at least four states: '0', '1', 'X', and 'Z'. In addition the states such as 'L' for a weak '1' signal or 'H' for a weak '1' signal are required to represent the TTL like buses based on prioritairy logic.

The multiple-sources signals require resolution function. This function should operate on a set of standard signal values.

All this requirement are fulfilled by the standard IEEE package called std_logic_1164 . The std_logic_1164 package introduces 9-valued logic covering all characteristic states of hardware signals. It also provides a resolution function which operates on 9-valued logic signals.

type std_ulogic is (



Standard numeric packages

The arithmetical operations (-,-,*, ..) cannot be used with the vector types such as bit_vector or std_logic_vector. The modeler must provide the arithmetic functions for binary or standard logic vectors and overload the existing operators. In order to facilitate this prepartion and to unify the numerical functions provided for the arithmetical operators, two standard packages have been developed.

These packages offer standard numeric operators actually integrated into the synthesis tools.

When using the numeric_bit package and numeric_std package ,the logical vectors are seen as unsigned or signed numbers.

  • unsigned - unsigned binary integer (two's-complement binary integer with the most significant bit on the left)
  • signed- signed binary integer (most significant bit on the left)
  • In addition the "numeric" packages provide necessary conversion functions such as:

    and the functions required to detect rising and falling edges of the signals



    Std_logic_1164 package

    Title : std_logic_1164 multi-value logic system

    Library : This package shall be compiled into a library symbolically named IEEE.

    Developers: IEEE model standards group (par 1164)

    Purpose : This packages defines a standard for designers to use in describing the interconnection data types used in vhdl modeling.

    Limitation: The logic system defined in this package may be insufficient for modeling switched transistors, since such a requirement is out of the scope of this effort. Furthermore, mathematics, primitives, timing standards, etc. are considered orthogonal issues as it relates to this package and are therefore beyond the scope of this effort.

    Note : No declarations or definitions shall be included in, or excluded from this package. The "package declaration" defines the types, subtypes and declarations of std_logic_1164. The std_logic_1164 package body shall be considered the formal definition of the semantics ofthis package. Tool developers may choose to implement the package body in the most efficient manner available to them


    PACKAGE std_logic_1164 IS

    -- logic state system (unresolved)

    TYPE std_ulogic IS (

    attribute ENUM_ENCODING of std_ulogic : type is "U D 0 1 Z D 0 1 D";
    -- unconstrained array of std_ulogic for use with the resolution function
    TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;
    -- resolution function
    FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
    attribute RESULT_INITIAL_VALUE of resolved: function is std_ulogic'POS('Z');
    -- *** industry standard logic type ***
    SUBTYPE std_logic IS resolved std_ulogic;
    unconstrained array of std_logic for use in declaring signal arrays
    TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;
    -- common subtypes
    SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1')
    SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z')
    SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1')
    SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z')
    -- overloaded logical operators
    FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
    FUNCTION "not" ( l : std_ulogic ) RETURN UX01;
    -- vectorized overloaded logical operators
    FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
    FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
    FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
    FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
    FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
    FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector;
    -- conversion functions
    FUNCTION To_bit ( s : std_ulogic ; xmap : BIT := '0' -) RETURN BIT;
    FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0' ) RETURN BIT_VECTOR;
    FUNCTION To_bitvector ( s : std_ulogic_vector ; xmap : BIT := '0' ) RETURN BIT_VECTOR;
    FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic;
    FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector;
    FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector;
    FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
    FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector;
    -- strength strippers and type convertors
    FUNCTION To_X01 ( s : std_ulogic ) RETURN X01;
    FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
    FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
    FUNCTION To_X01 ( b : BIT ) RETURN X01;
    FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
    FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z;
    FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector;
    FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
    FUNCTION To_X01Z ( b : BIT ) RETURN X01Z;
    FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector;
    FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
    FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01;
    FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
    FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
    FUNCTION To_UX01 ( b : BIT ) RETURN UX01;
    -- edge detection
    FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
    FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
    -- object contains an unknown
    FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN;
    FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN;
    FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN;
    END std_logic_1164;


    PACKAGE BODY std_logic_1164 IS
    -- local types
    TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
    TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
    -- resolution function
    CONSTANT resolution_table : stdlogic_table := (
    FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS
    VARIABLE result : std_ulogic := 'Z'; -- weakest state default
    BEGIN
    -- the test for a single driver is essential otherwise the loop would return 'X' for a single driver of '-' and that would conflict with the value of a single driver unresolved signal.
    IF (s'LENGTH = 1) THEN RETURN s(s'LOW);
    ELSE FOR i IN s'RANGE LOOP
    result := resolution_table(result, s(i));
    END LOOP; END IF;
    RETURN result;
    END resolved;
    -- tables for logical operations -
    -- truth table for "and" function
    CONSTANT and_table : stdlogic_table := (
    -- truth table for "or" function
    CONSTANT or_table : stdlogic_table := (
    -- truth table for "xor" function
    CONSTANT xor_table : stdlogic_table := (
    -- truth table for "not" function
    CONSTANT not_table: stdlogic_1d := (
    -- overloaded logical operators ( with optimizing hints )
    FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
    BEGIN
    END "and";
    FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
    BEGIN
    END "nand";
    FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
    BEGIN
    END "or";
    FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
    BEGIN
    END "nor";
    FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
    BEGIN
    END "xor";
    FUNCTION "not" ( l : std_ulogic ) RETURN UX01 IS
    BEGIN
    END "not";
    FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
    ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
    ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
    VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
    BEGIN
    IF ( l'LENGTH /= r'LENGTH ) THEN
    ELSE FOR i IN result'RANGE LOOP
    result(i) := and_table (lv(i), rv(i));
    END LOOP;
    END IF;
    RETURN result;
    END "and";
    FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
    ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
    ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
    VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
    BEGIN
    IF ( l'LENGTH /= r'LENGTH ) THEN
    ELSE FOR i IN result'RANGE LOOP
    result(i) := and_table (lv(i), rv(i));
    END LOOP;
    END IF;
    RETURN result;
    END "and";
    FUNCTION "nand" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
    ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
    ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
    VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
    BEGIN
    IF ( l'LENGTH /= r'LENGTH ) THEN
    ELSE FOR i IN result'RANGE LOOP
    result(i) := not_table(and_table (lv(i), rv(i)));
    END LOOP;
    END IF;
    RETURN result;
    END "nand";
    FUNCTION "nand" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
    ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
    ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
    VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
    BEGIN
    IF ( l'LENGTH /= r'LENGTH ) THEN
    ELSE FOR i IN result'RANGE LOOP
    result(i) := not_table(and_table (lv(i), rv(i)));
    END LOOP;
    END IF;
    RETURN result;
    END "nand";
    FUNCTION "or" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
    ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
    ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
    VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
    BEGIN
    IF ( l'LENGTH /= r'LENGTH ) THEN
    ELSE FOR i IN result'RANGE LOOP
    result(i) := or_table (lv(i), rv(i));
    END LOOP;
    END IF;
    RETURN result;
    END "or";
    FUNCTION "or" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
    ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
    ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
    VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
    BEGIN
    IF ( l'LENGTH /= r'LENGTH ) THEN
    ELSE FOR i IN result'RANGE LOOP
    result(i) := or_table (lv(i), rv(i));
    END LOOP;
    END IF;
    RETURN result;
    FUNCTION "nor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
    ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
    ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
    VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
    BEGIN
    IF ( l'LENGTH /= r'LENGTH ) THEN
    ELSE FOR i IN result'RANGE LOOP
    result(i) := not_table(or_table (lv(i), rv(i)));
    END LOOP;
    END IF;
    RETURN result;
    END "nor";
    FUNCTION "nor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
    ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
    ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
    VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
    BEGIN
    IF ( l'LENGTH /= r'LENGTH ) THEN
    ELSE FOR i IN result'RANGE LOOP
    result(i) := not_table(or_table (lv(i), rv(i)));
    END LOOP;
    END IF;
    RETURN result;
    END "nor";
    FUNCTION "xor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
    ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
    ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
    VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
    BEGIN
    IF ( l'LENGTH /= r'LENGTH ) THEN
    ELSE FOR i IN result'RANGE LOOP
    result(i) := xor_table (lv(i), rv(i));
    END LOOP;
    END IF;
    RETURN result;
    END "xor";
    FUNCTION "xor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
    ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
    ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
    VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
    BEGIN
    IF ( l'LENGTH /= r'LENGTH ) THEN
    ASSERT FALSE
    REPORT "arguments of overloaded 'xor' operator are not of the same length"
    SEVERITY FAILURE;
    ELSE FOR i IN result'RANGE LOOP
    result(i) := xor_table (lv(i), rv(i));
    END LOOP;
    END IF;
    RETURN result;
    END "xor";
    FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector IS
    ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
    VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
    BEGIN
    FOR i IN result'RANGE LOOP result(i) := not_table( lv(i) );
    END LOOP;
    RETURN result;
    END "not:
    FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector IS
    ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
    VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
    BEGIN
    FOR i IN result'RANGE LOOP
    result(i) := not_table( lv(i) );
    END LOOP;
    RETURN result;
    END;
    -- conversion tables
    TYPE logic_x01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01;
    TYPE logic_x01z_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01Z;
    TYPE logic_ux01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF UX01;
    -- table name : cvt_to_x01 parameters : in : std_ulogic
    -- some logic value
    -- returns : x01
    -- state value of logic value
    -- purpose : to convert state-strength to state only --
    -- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
    CONSTANT cvt_to_x01 : logic_x01_table := (
    -- table name : cvt_to_x01z
    -- parameters :
    -- in : std_ulogic -- some logic value
    -- returns : x01z -- state value of logic value
    -- purpose : to convert state-strength to state only --
    -- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
    CONSTANT cvt_to_x01z : logic_x01z_table := (
    ----------------------------------------------------------
    -- table name : cvt_to_ux01 --
    -- parameters :
    -- in : std_ulogic -- some logic value
    -- returns : ux01 -- state value of logic value
    -- purpose : to convert state-strength to state only --
    -- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
    CONSTANT cvt_to_ux01 : logic_ux01_table := (
    -- conversion functions
    FUNCTION To_bit ( s : std_ulogic ; xmap : BIT := '0' ) RETURN BIT IS
    BEGIN
    CASE s IS
    END CASE;
    END;
    FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0' ) RETURN BIT_VECTOR IS
    ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
    VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
    BEGIN
    FOR i IN result'RANGE LOOP CASE sv(i) IS
    END CASE;
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_bitvector ( s : std_ulogic_vector ; xmap : BIT := '0' ) RETURN BIT_VECTOR IS
    ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
    VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
    BEGIN
    FOR i IN result'RANGE LOOP
    CASE sv(i) IS
    END CASE;
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic IS
    BEGIN
    CASE b IS
    END CASE;
    END;
    FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector IS
    ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
    VARIABLE result : std_logic_vector ( b'LENGTH-1 DOWNTO 0 );
    BEGIN
    FOR i IN result'RANGE LOOP
    CASE bv(i) IS
    END CASE;
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector IS
    ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
    VARIABLE result : std_logic_vector ( s'LENGTH-1 DOWNTO 0 );
    BEGIN
    FOR i IN result'RANGE LOOP result(i) := sv(i);
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
    ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
    VARIABLE result : std_ulogic_vector ( b'LENGTH-1 DOWNTO 0 );
    BEGIN
    FOR i IN result'RANGE LOOP CASE bv(i) IS
    END CASE;
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector IS
    ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
    VARIABLE result : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 );
    BEGIN
    FOR i IN result'RANGE LOOP result(i) := sv(i);
    END LOOP;
    RETURN result;
    END;
    -- strength strippers and type convertors to_x01
    FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector IS
    ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
    VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
    BEGIN
    FOR i IN result'RANGE LOOP
    result(i) := cvt_to_x01 (sv(i));
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
    ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
    VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
    BEGIN
    FOR i IN result'RANGE LOOP result(i) := cvt_to_x01 (sv(i));
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS
    FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
    ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
    VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
    BEGIN
    FOR i IN result'RANGE LOOP
    CASE bv(i) IS
    END CASE;
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
    ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
    VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
    BEGIN
    FOR i IN result'RANGE LOOP
    CASE bv(i) IS
    END CASE;
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_X01 ( b : BIT ) RETURN X01 IS
    BEGIN
    CASE b IS
    END CASE;
    END;
    -- to_x01z
    FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector IS
    ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
    VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
    BEGIN
    FOR i IN result'RANGE LOOP
    result(i) := cvt_to_x01z (sv(i));
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
    ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
    VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
    BEGIN
    FOR i IN result'RANGE
    LOOP result(i) := cvt_to_x01z (sv(i));
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z IS
    BEGIN
    END;
    FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector IS
    ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
    VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
    BEGIN
    FOR i IN result'RANGE LOOP
    CASE bv(i) IS
    END CASE;
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
    ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
    VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
    BEGIN
    FOR i IN result'RANGE LOOP
    CASE bv(i) IS
    END CASE;
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_X01Z ( b : BIT ) RETURN X01Z IS
    BEGIN
    CASE b IS
    END CASE;
    END;
    -- to_ux01
    FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector IS
    ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
    VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
    BEGIN
    FOR i IN result'RANGE LOOP
    result(i) := cvt_to_ux01 (sv(i));
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
    ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
    VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
    BEGIN
    FOR i IN result'RANGE LOOP
    result(i) := cvt_to_ux01 (sv(i));
    END LOOP;
    RETURN result;
    URN UX01 IS
    BEGIN
    RETURN (cvt_to_ux01(s));
    END;
    FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
    ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b; VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
    BEGIN
    FOR i IN result'RANGE LOOP
    CASE bv(i) IS
    END CASE;
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
    ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
    VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
    BEGIN
    FOR i IN result'RANGE LOOP
    CASE bv(i) IS
    END CASE;
    END LOOP;
    RETURN result;
    END;
    FUNCTION To_UX01 ( b : BIT ) RETURN UX01 IS
    BEGIN
    CASE b IS
    END CASE;
    END;
    -- edge detection
    FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
    BEGIN
    END;
    FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
    BEGIN
    END;
    -- object contains an unknown
    FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN IS
    BEGIN FOR i IN s'RANGE LOOP
    CASE s(i) IS
    END CASE;
    END LOOP;
    RETURN FALSE;
    END;
    FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN IS
    BEGIN
    FOR i IN s'RANGE LOOP
    CASE s(i) IS
    END CASE;
    END LOOP;
    RETURN FALSE;
    END;
    FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN IS
    BEGIN
    CASE s IS
    END CASE;
    RETURN FALSE;
    END;
    END std_logic_1164;