VHDL : Switch level modeling

Switch level models are used to allow detailed construction of logical gates and functions and also to allow complex delay modeling to be used.

MOSFET switches

There are six different transistor models used in Verilog, nmos, pmos and cmos and the corresponding three resistive versions rnmos, rpmos and rcmos. The cmos type of switches have two gates and so have two control signals.

Syntax: keyword unique_name (drain. source, gate);

e.g.	nmos transistor1 (out, gnd, in);
	cmos transistor2 (out, gnd, in_n, in_p);		example 1

Resistive devices reduce the signal strength which appears on the output by one level.

All the switches only pass signals from source to drain, incorrect wiring of the devices will result in high impedance outputs.

Transmission gates

Syntax: keyword unique_name (inout1, inout2, control);

e.g.	tranif0 trans_gate1 (net5, net8, cnt);
	rtranif1 rtrans_gate2 (net5, net12, cnt);		example 2

Transmission gates tran and rtran are permently on and do not have a control line. Tran can be used to interface two wires with seperate drives, and rtran can be used to weaken signals.

Delays

Real transistors have resolution delays between the input and output. This is modeled in Verilog by specifying one or more delays for the rise, fall, turn-off and turn off time seperated by commas.

Syntax: keyword #(delay{s}) unique_name (node specifications);

e.g.	rnmos #(5,3,10) slow_nmos1 (out, gnd, in);		example 3

Note that the transmission gate primitives tran and rtran cannot be delayed because they never switch state.