First Look: Entities and Architectures

Every VHDL design description consists of at least one entity/architecture pair. (In VHDL jargon, this combination of an entity and its corresponding architecture is sometimes referred to as a design entity.) In a large design, you will typically write many entity/architecture pairs and connect them together to form a complete circuit.

An entity declaration describes the circuit as it appears from the "outside" - from the perspective of its input and output interfaces. If you are familiar with schematics, you might think of the entity declaration as being analogous to a block symbol on a schematic.

The second part of a minimal VHDL design description is the architecture declaration. Before simulation or synthesis can proceed, every referenced entity in a VHDL design description must be bound with a corresponding architecture. The architecture describes the actual function—or contents—of the entity to which it is bound. Using the schematic as a metaphor, you can think of the architecture as being roughly analogous to a lower-level schematic referenced by the higher-level functional block symbol.

Entity declaration

An entity declaration provides the complete interface for a circuit. Using the information provided in an entity declaration (the names, data types and direction of each port), you have all the information you need to connect that portion of a circuit into other, higher-level circuits, or to develop input stimuli (in the form of a test bench) for verification purposes. The actual operation of the circuit, however, is not included in the entity declaration.

Let’s take a closer look at the entity declaration for this simple design description:

entity compare is

port( A, B: in bit_vector(0 to 7);

EQ: out bit);

end compare;

The entity declaration includes a name, compare, and a port statement defining all the inputs and outputs of the entity. The port list includes definitions of three ports: A, B, and EQ. Each of these three ports is given a direction (either in, out or inout), and a type (in this case either bit_vector(0 to 7), which specifies an 8-bit array, or bit, which represents a single-bit value).

There are many different data types available in VHDL, and we will cover these types in more detail in other sections of this document. To simplify things in this introductory circuit, we’re going to stick with the simplest data types in VHDL, which are bit and bit_vector.

Architecture declaration and body

The second part of a minimal VHDL source file is the architecture declaration. Every entity declaration you reference in your design must be accompanied by at least one corresponding architecture (we’ll discuss why you might have more than one architecture in a moment).

Here’s the architecture declaration for the comparator circuit:

architecture compare1 of compare is

begin

EQ <= ‘1’ when (A = B) else ‘0’;

end compare1;

The architecture declaration begins with a unique name, compare1, followed by the name of the entity to which the architecture is bound, in this case compare. Within the architecture declaration (between the begin and end keywords) is found the actual functional description of our comparator. There are many ways to describe combinational logic functions in VHDL; the method used in this simple design description is a type of concurrent statement known as a conditional assignment. This assignment specifies that the value of the output (EQ) will be assigned a value of ‘1’ when A and B are equal, and a value of ‘0’ when they differ.

This single concurrent assignment demonstrates the simplest form of a VHDL architecture. As you will see, there are many different types of concurrent statements available in VHDL, allowing you to describe very complex architectures. Hierarchy and subprogram features of the language allow you to include lower-level components, subroutines and functions in your architectures, and a powerful statement known as a process allows you to describe complex registered sequential logic as well.