We’ll start this section by looking at a very simple combinational circuit: an 8-bit comparator. This comparator accepts two 8-bit inputs, compares them, and produces a 1-bit result (either 1, indicating a match, or 0, indicating a difference between the two input values).

 

A comparator such as this is a combinational function constructed in circuitry from an arrangement of exclusive-OR gates or from some other lower-level structure, depending on the capabilities of the target technology. When described in VHDL, however, a comparator can be a simple language statement that makes use of VHDL’s built-in relational operators.

 

Comparator source file

VHDL includes many high-level language features that allow you to describe combinational logic circuits. The following VHDL source code uses a single concurrent assignment to describe the operation of our comparator:

 

-- Eight-bit comparator

--

entity compare is

    port( A, B: in bit_vector(0 to 7);

             EQ: out bit);

end compare;

 

architecture compare1 of compare is

begin

 

    EQ <= ‘1’ when (A = B) else ‘0’;

 

end compare1;

 

Note: In this and other VHDL source files listed in this document, VHDL keywords are highlighted in bold face type. In some VHDL books and software documents, keywords are highlighted by using upper case characters for keywords and lower case characters for identifiers. Some other books and manuals use lower case for keywords and upper case for identifiers. Whatever forms you encounter or choose to use, keep in mind that VHDL itself is case-insensitive: keywords can be entered using either upper or lower case, and identifiers (such as signal and variable names) may be entered in either case as well, with no distinction being made between identifiers that are written in either case.

 

One more note: In the above context, the VHDL symbol <= is an assignment operator that assigns the value on its right to the signal on its left. Any text that follows "--" is a comment and is used for documentation only.

 

Now let’s look more closely at this source file. Reading from the top, we see the following elements:

 

•  An entity declaration that defines the inputs and outputs—the ports—of this circuit; and

•  An architecture declaration that defines what the circuit actually does, using a single concurrent assignment.