Example: Shifter

Shifter.VHD

-------------------------------------------------------
-- 8-bit barrel shifter
--
-- This example circuit demonstrates the behavior level
-- of abstraction. The operation of the barrel shifter
-- is described as the circuit's response to stimulus
-- (such as clock and reset events) over time.
--
-- This circuit is synthesizable. To test the circuit with
-- the supplied test bench (testshif.vhd), be sure to
-- compile this source file into library 'work'.
--
-- Copyright 1995, Accolade Design Automation, Inc.
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity shifter is
    port( Clk, Rst, Load: in std_ulogic;
          Data: std_ulogic_vector(0 to 7);
          Q: out std_ulogic_vector(0 to 7));
end shifter;
 
architecture behavior of shifter is
begin
    -- We use a process to describe the operation of
    -- the shifter over time, in response to its inputs...
    reg: process(Rst,Clk)
        -- Using a variable simplifies register feedback...
        variable Qreg: std_ulogic_vector(0 to 7);
    begin
        if Rst = '1' then   -- Async reset
            Qreg := "00000000";
        elsif rising_edge(Clk) then
            if Load = '1' then
                Qreg := Data;
            else
                Qreg := Qreg(1 to 7) & Qreg(0);
            end if;
        end if;
        Q <= Qreg;
    end process;
end behavior;
 

Testshif.VHD

-------------------------------------------------------
-- Test bench for 8-bit barrel shifter
--
-- Copyright 1995, Accolade Design Automation, Inc.
--
library ieee; use ieee.std_logic_1164.all;
use work.all;    -- Get the shifter out of library 'work'
 
entity testrot is
end testrot;
 
architecture stimulus of testrot is
    component shifter
        port(Clk, Rst, Load: in std_ulogic;
             Data: std_ulogic_vector(0 to 7);
             Q: out std_ulogic_vector(0 to 7));
    end component;
--
    constant PERIOD: time := 40 ns;
--
    signal Clk,Rst,Load: std_ulogic;
    signal Data: std_ulogic_vector(0 to 7);
    signal Q: std_ulogic_vector(0 to 7);
--
begin
    DUT: shifter port map(Clk,Rst,Load,Data,Q);
 
    -- This test bench uses two processes to describe
    -- the stimulus.  This first process describes a
    -- constantly running clock of 40 ns cycle time...
    CLOCK: process
    begin
        Clk <= '1';
        wait for PERIOD / 2;
        Clk <= '0';
        wait for PERIOD / 2;
    end process;
    -- This process applies a sequence of inputs to the
    -- circuit to exercise this shift and load features...
    INPUTS: process
    begin
        wait for PERIOD / 2;
        Rst <= '1';
        Data <= "00000000";
        Load <= '0';
        wait for PERIOD;
        Rst <= '0';
        wait for PERIOD;
        Data <= "00001111";
        Load <= '1';
        wait for PERIOD;
        Load <= '0';
        wait for PERIOD * 4;
        Rst <= '1';
        Data <= "00000000";
        Load <= '0';
        wait for PERIOD;
        Rst <= '0';
        wait for PERIOD;
        Data <= "10101010";
        Load <= '1';
        wait for PERIOD;
        Load <= '0';
        wait for PERIOD * 4;
         Rst <= '1';
        Data <= "00000000";
        Load <= '0';
        wait for PERIOD;
        Rst <= '0';
        wait for PERIOD;
        Data <= "10000001";
        Load <= '1';
        wait for PERIOD;
        Load <= '0';
        wait for PERIOD * 4;
        wait;
     end process;
end stimulus;