Example: Tcount

Tcount.VHD

-------------------------------------------------------
-- Structural description of a fast and efficient T
-- flip-flop counter.
--
-- This example demonstrates the use of component port
-- maps and default interfaces.
--
-- Copyright 1997, Accolade Design Automation, Inc.
--
library ieee;
use ieee.std_logic_1164.all;
 
entity andgate is
    port(A,B,C,D: in std_ulogic := '1';
         Y: out std_ulogic);
end andgate;
 
architecture gate of andgate is
begin
    Y <= A and B and C and D;
end gate;
 
use ieee.std_logic_1164.all;
entity tff is
    port(Rst,Clk,T: in std_ulogic;
         Q: out std_ulogic);
end tff;
 
architecture behavior of tff is
begin
    process(Rst,Clk)
        variable Qtmp: std_ulogic;
    begin
        if (Rst = '1') then
            Qtmp := '0';
        elsif rising_edge(Clk) then
            if T = '1' then
                Qtmp := not Qtmp;
            end if;
        end if;
        Q <= Qtmp;
    end process;
end behavior;
 
use ieee.std_logic_1164.all;
entity TCOUNT is
    port (Rst: in std_ulogic;
          Clk: in std_ulogic;
          Count: out std_ulogic_vector(4 downto 0)
    );
end TCOUNT;
 
architecture STRUCTURE of TCOUNT is
    component tff
        port(Rst,Clk,T: in std_ulogic;
             Q: out std_ulogic);
    end component;
    component andgate
        port(A,B,C,D: in std_ulogic := '1';
             Y: out std_ulogic);
    end component;
    constant VCC: std_ulogic := '1';
    signal T,Q: std_ulogic_vector(4 downto 0);
begin
    T(0) <= VCC;
    T0: tff port map (Rst=>Rst, Clk=>Clk, T=>T(0), Q=>Q(0));
    T(1) <= Q(0);
    T1: tff port map (Rst=>Rst, Clk=>Clk, T=>T(1), Q=>Q(1));
    A1: andgate port map(A=>Q(0), B=>Q(1), Y=>T(2));
    T2: tff port map (Rst=>Rst, Clk=>Clk, T=>T(2), Q=>Q(2));
    A2: andgate port map(A=>Q(0), B=>Q(1), C=>Q(2), Y=>T(3));
    T3: tff port map (Rst=>Rst, Clk=>Clk, T=>T(3), Q=>Q(3));
    A3: andgate port map(A=>Q(0), B=>Q(1), C=>Q(2), D=>Q(3), Y=>T(4));
    T4: tff port map (Rst=>Rst, Clk=>Clk, T=>T(4), Q=>Q(4));
 
    Count <= Q;
 
end STRUCTURE;
 

T_tcount.VHD

-------------------------------------------------------
-- Auto-generated test bench for TCOUNT
--
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.all;
 
entity TESTBNCH is
end TESTBNCH;
 
architecture stimulus of TESTBNCH is
component TCOUNT
    port (
        Rst: in std_ulogic;
        Clk: in std_ulogic;
        Count: out std_ulogic_vector(4 downto 0)
    );
end component;
constant PERIOD: time := 100 ns;
-- Top level signals go here...
signal Rst: std_ulogic;
signal Clk: std_ulogic;
signal Count: std_ulogic_vector(4 downto 0);
signal done: boolean := false;
 
for DUT: TCOUNT use entity work.TCOUNT(STRUCTURE);
 
begin
    DUT: TCOUNT port map (
            Rst => Rst,
            Clk => Clk,
            Count => Count
          );
 
    CLOCK1: process
        variable clktmp: std_ulogic := '0';
    begin    
        wait for PERIOD/2;
        clktmp := not clktmp;
        Clk <= clktmp;  -- Attach your clock here
        if done = true then
            wait;
        end if;
    end process;
 
    STIMULUS1: process
    begin
 
        -- Sequential stimulus goes here...
 
        Rst <= '1';
        wait for PERIOD;
 
        Rst <= '0';
 
        wait for PERIOD * 36;
 
        done <= true;
        wait;
    end process;
 
end stimulus;