Process window

The Process window displays a list of processes. If View > Active is selected then all processes scheduled to run during the current simulation cycle are displayed along with the pathname of the instance in which each process is located. If View > In Region is selected then only the processes in the currently selected region are displayed.

Each HDL item in the scrollbox is preceded by one of the following indicators:

• <Ready>
  Indicates that the process is scheduled to be executed within the current delta time.
• <Wait>
  Indicates that the process is waiting for a VHDL signal or Verilog net or variable to change or for a specified time-out period.
• <Done>
  Indicates that the process has executed a VHDL wait statement without a time-out or a sensitivity list. The process will not restart during the current simulation run.

If you select a "Ready" process, it will be executed next by the simulator.

When you click on a process in the Process window, the following windows are updated:

Window updated	Result
Structure window	shows the region in which the process is located
Variables window	shows the VHDL variables and Verilog register variables in the process
Source window	shows the associated source code
Dataflow window	shows the process, the signals, nets, and registers the process reads, and the signals, nets, and registers driven by the process
Source window	shows the signals, nets, and registers declared in the region in which the process is located

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