SDF specification with the GUI

As an alternative to the command-line options, you can specify SDF files in the Load Design dialog box under the SDF tab.

You can access this dialog by invoking the simulator without any arguments or by selecting Design > Load Design (Main window). For Verilog designs, you can also specify SDF files by using the $sdf_annotate system task. See "The $sdf_annotate system task" for more details.

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