vcd add

The vcd add command adds the specified items to a VCD file. The allowed items are Verilog nets and variables and VHDL signals of type bit, bit_vector, std_logic, and std_logic_vector (other types are silently ignored).

All vcd add commands must be executed at the same simulation time. The specified items are added to the VCD header and their subsequent value changes are recorded in the specified VCD file.

By default all port driver changes and internal variable changes are captured in the file. You can filter the output using arguments detailed below.

Related Verilog tasks: $dumpvars, $fdumpvars

Syntax

vcd add

[-r] [-in] [-out] [-inout] [-internal] [-ports] [-file <filename>] <item_name>

Arguments

-r

Specifies that signal and port selection occurs recursively into subregions. Optional. If omitted, included signals and ports are limited to the current region.

-in

Includes only port driver changes from ports of mode IN. Optional.

-out

Includes only port driver changes from ports of mode OUT. Optional.

-inout

Includes only port driver changes from ports of mode INOUT. Optional.

-internal

Includes only internal variable or signal changes. Excludes port driver changes. Optional.

-ports

Includes only port driver changes. Excludes internal variable or signal changes. Optional.

-file <filename>

Specifies the name of the VCD file. This option should be used only when you have created multiple VCD files using the vcd files command.

<item_name>

Specifies the Verilog or VHDL item to add to the VCD file. Required. Multiple items may be specified by separating names with spaces. Wildcards are accepted.

See also

See Value Change Dump (VCD) Files chapter for more information on VCD files. Verilog tasks are documented in the IEEE 1364 standard.

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