vcom

The vcom command is used to invoke VCOM, the Model Technology VHDL compiler. Use VCOM to compile VHDL source code into a specified working library (or to the work library by default).

This command may be invoked from within ModelSim or from the operating system command prompt. This command may also be invoked during simulation.

Syntax

vcom

[-87] [-93] [-check_synthesis] [-debugVA] [-defercheck]
[-explicit] [-f <filename>] [-force_refresh] [-help]
[-ignoredefaultbinding] [-ignorevitalerrors] [-just eapbc] [-skip eapbc] [-line <number>] [-no1164] [-noaccel <package_name>] [-nocasestaticerror]
[-noothersstaticerror] [-nocheck] [-nodebug[=ports]] [-nolock] [-nologo]
[-novital] [-novitalcheck] [nowarn <number>] [-O0 | -O1 | -O4 | -O5]
[-pedanticerrors] [-performdefaultbinding] [-quiet] [-rangecheck]
[-refresh] [-s] [-source] [-version] [-vital2000] [-work <library_name>] <filename>

Arguments

-87

Disables support for VHDL 1076-1993. This is the VCOM default. Optional. See additional discussion in the examples. Note that the default can be changed with the modelsim.ini file; see "Preference variables located in INI files" .

-93

Specifies that the simulator is to support VHDL 1076-1993. Optional. Default is -87. See additional discussion in the examples.

-check_synthesis

Turns on limited synthesis rule compliance checking. Optional. Checks to see that signals read by a process are in the sensitivity list.

-debugVA

Prints a confirmation if a VITAL cell was optimized, or an explanation of why it was not, during VITAL level1 acceleration. Optional.

-defercheck

Defers until run-time all compile-time range checking on constant index and slice expressions . As a result, index and slice expressions with invalid constant ranges that are never evaluated will not cause compiler error messages to be issued. Optional.

-explicit

Directs the compiler to resolve ambiguous function overloading by favoring the explicit function definition over the implicit function definition. Optional. Strictly speaking, this behavior does not match the VHDL standard. However, the majority of EDA tools choose explicit operators over implicit operators. Using this switch makes ModelSim compatible with common industry practice.

-f <filename>

Specifies a file with more command line arguments. Allows complex arguments to be reused without retyping. Optional.

-force_refresh

Forces the refresh of a module. Optional. When the compiler refreshes a design unit, it checks each module's dependencies to ensure its source has not been changed and recompiled. If the source has been changed and recompiled, the compiler will not refresh the dependent module (unless you use the force_refresh switch). To avoid potential syntax errors caused by the source change, you should recompile the modified source rather than use this switch.

-help

Displays the command's options and arguments. Optional.

-ignoredefaultbinding

Instructs the compiler not to generate a default binding during compilation. Optional. You must explicitly bind all components in the design to use this switch.

-ignorevitalerrors

Directs the compiler to ignore VITAL compliance errors. Optional. The compiler still reports that VITAL errors exist, but it will not stop the compilation. You should exercise caution in using this switch; as part of accelerating VITAL packages, we assume that compliance checking has passed.

-just eapbc

Directs the compiler to "just" include:
e - entities
a - architectures
p - packages
b - bodies
c - configurations

Any combination in any order can be used, but one choice is required if you use this optional switch.

-skip eapbc

Directs the compiler to skip all:
e - entities
a - architectures
p - packages
b - bodies
c - configurations

Any combination in any order can be used, but one choice is required if you use this optional switch.

-line <number>

Starts the compiler on the specified line in the VHDL source file. Optional. By default, the compiler starts at the beginning of the file.

-no1164

Causes the source files to be compiled without taking advantage of the built-in version of the IEEE std_logic_1164 package. Optional. This will typically result in longer simulation times for VHDL programs that use variables and signals of type std_logic.

-noaccel <package_name>

Turns off acceleration of the specified package in the source code using that package.

-nocasestaticerror

Suppresses case static warnings. Optional. VHDL standards require that case alternative choices be static at compile time. However, some expressions which are globally static are allowed. This switch prevents the compiler from warning on such expressions. If the pedanticerrors switch is specified, this switch is ignored.

-noothersstaticerror

Disables warnings that result from array aggregates with multiple choices having "others" clauses that are not locally static. Optional. If the -pedanticerrors switch is specified, this switch is ignored.

-nocheck

Disables run time range checking. Default. In some designs, this results in a 2X speed increase. Range checking can be enabled using -rangecheck.

-nodebug[=ports]

Hides the internal data of the compiled design unit. Optional. The design unit's source code, internal structure, signals, processes, and variables will not display in ModelSim's windows. In addition, none of the hidden objects may be accessed through the Dataflow window or with commands. This also means that you cannot set breakpoints or single step within this code. Don't compile with this switch until you're done debugging.

Note that this is not a speed switch like the "nodebug" option on many other products.

The optional =ports switch hides the ports for the lower levels of your design; it should only be used to compile the lower levels of the design. If you hide the ports of the top level you will not be able to simulate the design.

Note: -nodebug provides protection for proprietary model information. The Verilog 'protect compiler directive provides similar protection, but uses a Cadence encryption algorithm that is unavailable to Model Technology.

Design units or modules compiled with -nodebug can only instantiate design units or modules that are also compiled -nodebug.

See additional discussion in "Source code security and -nodebug" .

-nolock

Overrides the library lock file. Optional. Default is locked. The lock file prevents multiple users from concurrently accessing the same library. If you are a single user, disabling the lock file should not present a problem. However, using this switch can lead to a corrupt library if multiple compiles are run on the same library at the same time.

-nologo

Disables startup banner. Optional.

-novital

Causes VCOM to use VHDL code for VITAL procedures rather than the accelerated and optimized timing and primitive packages built into the simulator kernel. Optional.

-novitalcheck

Disables VITAL95 compliance checking if you are using VITAL 2.2b. Optional.

nowarn <number>

Selectively disables an individual warning message. Optional. Multiple nowarn switches are allowed. Warnings may be disabled for all compiles via the modelsim.ini file (see the "[vcom] VHDL compiler control variables" ).

The warning message numbers are:

1 = unbound component
2 = process without a wait statement
3 = null range
4 = no space in time literal
5 = multiple drivers on unresolved signal
6 = compliance checks
7 = optimization messages 

-O0 | -O1 | -O4 | -O5

Lower the optimization to a minimum with -O0 (capital oh zero). Optional. Use this to work around bugs, increase your debugging visibility on a specific cell, or when you want to place breakpoints on source lines that have been optimized out.

Enable PE-level optimization with -O1. Optional.

Enable standard SE optimizations with -O4. Default.

Enable maximum optimization with -O5. Optional. Use caution with this switch. We recommend use of this switch with large sequential blocks only, other uses may significantly increase compile times. Optional.

-pedanticerrors

Forces ModelSim to error (rather than warn) on two conditions: 1) when a choice in a case statement is not a locally static expression; 2) when an array aggregate with multiple choices doesn't have a locally static "others" choice. Optional. This argument overrides -nocasestaticerror and -noothersstaticerror (see above).

-performdefaultbinding

Enables default binding when it has been disabled via the RequireConfigForAllDefaultBinding option in the modelsim.ini file. Optional.

-quiet

Disable 'loading' messages. Optional.

-rangecheck

Enables run time range checking. Range checks are disabled by default. Once enabled, they can be disabled using -nocheck argument.

-refresh

Regenerates a library image. Optional. By default, the work library is updated; use -work <library> to update a different library. See vcom "Examples" for more information.

-s

Instructs the compiler not to load the standard package. Optional. This argument should only be used if you are compiling the standard package itself.

-source

Displays the associated line of source code before each error message that is generated during compilation. Optional; by default, only the error message is displayed.

-version

Returns the version of the compiler as used by the licensing tools, such as "Model Technology ModelSim SE vcom 5.5 Compiler 2000.01 Jan 29 2000".

-vital2000

Turns on acceleration of vital_memory package in VITAL 2000 library. Optional.

-work <library_name>

Specifies a logical name or pathname of a library that is to be mapped to the logical library work. Optional; by default, the compiled design units are added to the work library. The specified pathname overrides the pathname specified for work in the project file.

<filename>

Specifies the name of a file containing the VHDL source to be compiled. One filename is required; multiple filenames can be entered separated by spaces or wildcards may be used, i.e., "*.vhd".

Examples

vcom example.vhd

Compiles the VHDL source code contained in the file example.vhd.

vcom -87 o_units1 o_units2
vcom -93 n_unit91 n_unit92

ModelSim supports designs that use elements conforming to both the 1993 and the 1987 standards. Compile the design units separately using the appropriate switches.

Note that in the example above, the -87 switch on the first line is redundant since the VCOM default is to compile to the 1987 standard.

vcom -nodebug example.vhd

Hides the internal data of example.vhd. Models compiled with -nodebug cannot use any of the ModelSim debugging features; any subsequent user will not be able to see into the model.

vcom -nodebug=ports level3.vhd levle2.vhd
vcom -nodebug top.vhd

The first line compiles and hides the internal data, plus the ports, of the lower-level design units, level3.vhd and level2.vhd. The second line compiles the top-level unit, top.vhd, without hiding the ports. It is important to compile the top level without =ports because top-level ports must be visible for simulation.

See "Source code security and -nodebug" for more details.

vcom -noaccel numeric_std example.vhd

When compiling source that uses the numeric_std package, this command turns off acceleration of the numeric_std package, located in the ieee library.

vcom -explicit example.vhd

Although it is not obvious, the = operator is overloaded in the std_logic_1164 package. All enumeration data types in VHDL get an "implicit" definition for the = operator. So while there is no explicit = operator, there is an implicit one. This implicit declaration can be hidden by an explicit declaration of = in the same package (LRM Section 10.3). However, if another version of the = operator is declared in a different package than that containing the enumeration declaration, and both operators become visible through use clauses, neither can be used without explicit naming.

ARITHMETIC."="(left, right) 

To eliminate that inconvenience, the VCOM command has the -explicit option that allows the explicit = operator to hide the implicit one. Allowing the explicit declaration to hide the implicit declaration is what most VHDL users expect.

vcom -work mylib -refresh

The work option specifies mylib as the library to regenerate. refresh rebuilds the library image without using source code, allowing models delivered as compiled libraries without source code to be rebuilt for a specific release of ModelSim (4.6 and later only).

If your library contains Verilog design units be sure to regenerate the library with vlog and refresh as well. See "Regenerating your design libraries" for more information.

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