check contention add
The check contention add command enables contention checking for the specified nodes. The allowed nodes are Verilog nets and VHDL signals of std_logic and std_logic_vector. Any other node types and nodes that don't have multiple drivers are silently ignored by the command.
Syntax
check contention add
[
-r] [
-in] [
-out] [
-inout] [
-internal] [
-ports]
<node_name>Arguments
-r
Specifies that contention checking is enabled recursively into subregions. Optional; if omitted, contention check enabling is limited to the current region.
-in
Enables checking on nodes of mode IN. Optional.
-out
Enables checking on nodes of mode OUT. Optional.
-inout
Enables checking on nodes of mode INOUT. Optional.
-internal
Enables checking on internal items. Optional.
-ports
Enables checking on nodes of modes IN, OUT, or INOUT. Optional.
<node_name>
Enables checking for the named node(s). Required.
See also
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