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Lesson 4 - Debugging a VHDL design
The goals for this lesson are:
- Show an example of a VHDL testbench - a VHDL architecture that instantiates the VHDL design units to be tested, provides simulation stimuli, and checks the results
- Map a logical library name to an actual library
- Change the default run length
- Recognize assertion messages in the command window
- Change the assertion break level
- Restart the simulation run using the restart command
- Examine composite types displayed in the Variables window
- Change the value of a variable
- Use a strobe to trigger lines in the List window
- Change the radix of signals displayed in the List window
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