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Running the simulation
- Now it's time to simulate. Start the simulator by selecting the Load Design button from the Main toolbar:
This returns the Load Design dialog box.
On the Design tab select the top entity and click Load.
- This time you will use the command line to add all of the HDL items in the region to the List and Wave windows:
add list * add wave *(Signals MENU: View > List > Signals in Region)
(Signals MENU: View > Wave > Signals in Region)Notice the hierarchical mixture of VHDL and Verilog in the design. VHDL levels are indicated by a square "prefix", while Verilog levels are indicated by a circle "prefix." Try expanding (+) and contracting (-) the structure layers. You'll find Verilog modules have been instantiated by VHDL architectures, and similar instantiations of VHDL items by Verilog.
Let's take another look at the design.
- In the Structure pane, click on the Verilog module c: cache. The source code for the Verilog module is now shown in the Source window.
- We'll use ModelSim's Find function to locate the declaration of cache_set within cache.v.
From the Source window menu select: Edit > Find:
The Find in dialog box is displayed.
In the Find: field, type cache_set and click Find Next. The cache_set instantiations are now displayed in the Source window. (Click Close to dismiss the Find in: dialog box.)
Note that cache_set is a VHDL entity instantiated within the Verilog file cache.v.
- Now click on the line "s0: cache_set(only)" in the Structure window. If instance s0 is not currently visible, click on the + next to c:cache.
The Source window shows the VHDL code for the cache_set entity.
Before you quit, try experimenting with some of the commands you've learned from Lesson 1. Note that in this design, "clk" is already driven, so you won't need to use the force command.
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