Preparing the simulation

1. Start by creating a new directory for this exercise. Create the directory, then copy the VHDL and Verilog example files to the directory:



<install_dir>\modeltech\examples\mixedHDL\*.vhd 
<install_dir>\modeltech\examples\mixedHDL\*.v  

Make sure the new directory is the current directory. Do this by invoking ModelSim from the new directory or by using the File > Change Directory command from the ModelSim Main window.

2. Start ModelSim with one of the following:

for UNIX at the shell prompt:

vsim -gui 

for Windows - your option - from a Windows shortcut icon, from the Start menu, or from a DOS prompt:

modelsim.exe





 

 
Note: If you didn't add ModelSim to your search path during installation, you will have to include the full path when you type this command at a DOS prompt.



 

Select "Proceed to ModelSim" if the Welcome dialog appears.

3. Select Design > Create a New Library to create a new library to hold the mixed design.
   (PROMPT: vlib work)
   



Type "work" in the Library Name field and then select OK.

This creates a subdirectory named work (your design library) within the current directory and a logical mapping to the library. The library contains a special file named _info that is created with the library.

Important: Do not create library subdirectories using UNIX or Windows commands-always use the Design menu or the vlib command from either the ModelSim or UNIX/DOS prompt.

4. Compile the HDL files by selecting the Compile button on the toolbar:




(PROMPT: vlog cache.v memory.v proc.v)

(PROMPT: vcom util.vhd set.vhd top.vhd)

This opens the Compile HDL Source Files dialog box.



A group of Verilog files can be compiled in any order. Note, however, in a mixed VHDL/Verilog design the Verilog files must be compiled before the VHDL files.

Compile the source by double-clicking each of these Verilog files in the file list (this invokes the Verilog compiler, vlog):

• cache.v
• memory.v
• proc.v

5. Depending on the design, the compile order of VHDL files can be very specific. In the case of this lesson, the file top.vhd must be compiled last.

Stay in the Compile HDL Source Files dialog box and compile the VHDL files in this order (this invokes the VHDL compiler, vcom):

• util.vhd
• set.vhd
• top.vhd

6. Compiling is now complete, click Done to dismiss the dialog box.

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