Lesson 4 - Mixed VHDL/Verilog simulation

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The goals for this lesson are:

• Compile multiple VHDL and Verilog files
• Simulate a mixed VHDL and Verilog design
• List VHDL signals and Verilog nets and registers
• View the design in the Structure window
• View the HDL source code in the Source window

Note: You must be using ModelSim SE/PLUS or ModelSim SE/MIXED to do this lesson.

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