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Lesson 3 - Basic Verilog simulation
The goals for this lesson are:
- Compile a Verilog design
- List signals in the design
- Examine the hierarchy of the design
- Simulate the design
- Change list attributes
- Set a breakpoint
The project feature covered in Lesson 1 executes several actions automatically such as creating and mapping work libraries. In this lesson we will go through the whole process so you get a feel for how ModelSim really works.
 Model Technology Incorporated Voice: (503) 641-1340 Fax: (503)526-5410 www.model.com sales@model.com |
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