The Free-6502 core comes with some development tools. These tools are:
 | MCGEN -- Converts the microcode.csv file into VHDL and Verilog source code. |
| ROM2VHDL -- Converts a raw binary file into a synthesizeable VHDL ROM. |
These tools were compiled using GCC on a Windows NT machine. They should run on any current Windows platform, but if not (or if you're not running Windows) the C source code is provided in the distribution. The C is fairly generic and should be very easy to port to different compilers and platforms.
For those who are very interested, we used the Cygwin port of the GNU tools to Windows NT. These provide all of the UNIX tools, including GCC, make, etc. This will be the standard tool set used for all Free-IP Projects.
MCGEN
The Free-6502 microcode was written using Microsoft Excel. It sounds strange, but it worked out very well and was a whole lot easier than writing it directly in VHDL. The main microcode is in the file microcode.xls. Before using MCGEN to make the VHDL source code, this must be converted to microcode.csv. Do this by selecting "Save as" from the Excel menus and changing the file type to *.csv.
For those who are wondering, a CSV file is ASCII text and easily parsed. The XLS files are not ASCII, but are a complex format used by Excel. XLS files have lots of formatting information in them that makes them more human readable than CSV files. That's why we edit the XLS files, but require a CSV to generate the final microcode VHDL and Verilog source code.
In the MCGEN directory, there is a makefile that will compile the mcgen.c file and also generate microcode.vhd. There are many ways to run the make file, but here are the ones that will be most useful.
make -- Makes mcgen.exe and microcode.vhd
make all -- Same as just "make"
make mcgen.exe -- makes just, well, mcgen.exe
make microcode -- makes just the microcode.vhd file
make clean -- deletes the mcgen.exe and microcode.vhd files
The Verilog version of this program works the same way, but make Verilog.
ROM2VHDL
This utility takes a raw binary file and a template file as an input and generates VHDL source code. This is a complicated program to explain, but the operation is simple enough.
The template file is basically VHDL source code with special commands embedded into it. These commands tell ROM2VHDL where to put the ROM and how to format the ROM. The commands are:
--addrbits <# of bits>
This command sets the number of bits to use for the address. The valid range of bits is 2 to 32 bits.--databits <# of bits>
Sets the number of data bits. Valid values are 8, 16, 24, and 32 bits.--varname <name>
Sets the signal/variable name used for the "data bus".--big-endian
Configures ROM2VHDL for big endian input files.--little-endian
Configures ROM2VHDL for little endian input files.--start_of_rom
Signals the start of ROM. ROM2VHDL will place the body of the case statement after this command.--end_of_rom
Signals the end of the ROM.
One important thing about ROM2VHDL is that the input template is passed verbatim to the output file, with the exception of everything between --start_of_rom and --end_of_rom. Between those two markers, everything in the template file is ignored and removed. So, write your template file accordingly.
A good example of how ROM2VHDL is used is in the /code/testsuite directory of the Free-6502 distribution.
