CATEGORY: [ ][ ][ ][ ][ ][ HDL ]
Part 1 | Part 2 | Part 3 - Papers | Part 4 | Part 5
- John Kent's Home Page (2013.7.26)
- 출처: http://members.optushome.com.au/jekent/...
- HDL Archives Part 2에 있는 내용의 update version입니다.
- Thorsten Gärtner - Homepage (2013.8.27)
- 출처: http://www.thorsten-gaertner.de/vhdl/vhdl.htm
- VHDL - Moduls (only english)
- PRBS - Generator and Receiver
- E2 - Framer / Deframer (according ITU-T G.703 / G.742)
- E3 - Framer / Deframer (according ITU-T G.703 / G.751)
- E3 - Mux / Demux - Multiplexer of 16 E1 Channels (according ITU-T G.703 / G.742 / G.751)
- VCO - Voltage Controlled Oscillator
- Memory Cores (2013.9.9)
- 출처: http://www.geocities.com/SiliconValley/Pines/6639/ip/memory_cores.html (폐쇄됨)
- The aim of this project is to develop generic synthesizable memory cores. Most of the cores are synthesized on different FPGAs and gave good results.
- Free-6502, Version 0.7 (2013.9.9)
- The Free-6502 core is a 6502 compatible CPU core.
- 기존 free-ip.com에서 제공하던 내용이었으나, 지난 2005.07.13. 해당 domain이 만료가 되어 더 이상 관련내용을 찾아볼 수 없게 된 관계로 이곳에서 mirroring합니다.
- README.TXT 파일 보기.
- F-CPU (Freedom CPU) website, (2013.10.6)
- 출처: http://f-cpu.seul.org/...
- The Freedom CPU Project is an open work of collaboration in the world of microelectronics. Our goal is to create and distribute the source code of a high performance microprocessor core under a copyleft license.
2.References / Manuals / Papers
- Verilog Hardware Description Language (2014.3.17)
- The material here consists of relics from an ancient EPSRC project by David Greaves and Mike Gordon entitled Checking Equivalence Between Synthesised Logic and Non-Synthesisable Behavioural Prototypes.
std_logic libraries reference (2014.6.2)
- 출처: http://www.cs.sfu.ca/~ggbaker/reference/std_logic/
- Synopsys FPGA Express Verilog-HDL Reference Manual, December 1997 (2015.9.4)
- Synopsys FPGA Express VHDL Reference Manual, December 1997 (2015.9.4)
- Synopsys FPGA Express Verilog-HDL Reference Manual, v1999.05, May 1999 (2016.3.21)
- Synopsys FPGA Express VHDL Reference Manual, v1999.05, May 1999 (2016.3.21)
- VHDL Library of Arithmetic Units, Reto Zimmermann, Integrated Systems Laboratory, Swiss Federal Institute of Technology (ETH) Zurich, Switzerland (2015.9.24)
- VHDL: numeric (IEEE) packages and std_logic (SYNOPSYS) packages (2015.10.1)
3.Text Books / Tutorials / Courses
Digital Logic and Microprocessor Design with VHDL (2014.3.9)
- Course guideline
- INTRODUCTION TO CALD (Computer Aided Logic Design)
- The Logic Circuit CAD Process
- Hardware Description Languages (HDLs) - Altera Hardware Description Language (AHDL) & VHDL (Very High Speed Integrated Circuit Hardware Description Language)
- Enoch Hwang Ph.D., Computer Science Department, La Sierra University
Digital Design with RTL Design, VHDL, and Verilog (2014.3.10)
- Second Edition, by Frank Vahid, University of California, Riverside
- John Wiley and Sons Publishers, 2011
LAB in Chip Design 203.4260 203.3260 (Yosi Ben Asher) (2014.3.17)
- 출처: The Department of Computer Science at the University of Haifa
- Verilog-HDL 교육용 slide들이 있습니다.
VHDL and System-on-Chip, IAX8165 5.0 AP 4 3-2-0 E (2014.3.18)
ALDEC, Active-HDL 7.3 Training Material (include CADSTAR interfacing) (2014.5.30)
EEL 4783: Hardware/Software Co-design with FPGAs (2014.6.5)
- ALDEC Corporate Overview
- Introduction to Active-HDL
- Design Entry Methods
- Efficient Design Management
- Design Verification – Running Simulation
- Design Verification- Debugging
- Synthesis and Implementation in Flow Manager
- Using the PCB interface
- 출처: http://www.eecs.ucf.edu/~mingjie/EEL4783_2012/
Verilog-HDL 강좌 (네이버 블로그) (2014.6.12)
Practical Problems in VLSI Physical Design Automation (2014.7.11)
- by Lim, Sung Kyu, Georgia Institute of Technology, Atlanta, GA, USA / Springer, 2008
- Georgia Tech에서 학생들을 가르치고 계신 임성규 박사께서 쓰신 책의 companion page입니다. 교재로서 활용하는데 도움이 되는 몇몇 resource들이 제공됩니다.
CDA 3200 Spring 2012, Digital Systems (2015.1.19)
- Dr. Janusz Zalewski, Florida Gulf Coast University
- Course Syllabus
- List of Class Modules: Spring 2012
FPGA Synthesis with the Synplify Pro Tool (2015.5.20)
Companion Materials for Dr. Chu's books (2015.4.7)
- by Dr. Pong P. Chu (Department of Electrical and Computer Engineering, Cleveland State University)
- 출처: http://academic.csuohio.edu/chu_p/rtl/
ELEC 516 Digital VLSI System Design and Design Automation (Spring,2010) (2015.9.19)
- RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Salability
- FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version
- FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version
- Embedded SoPC Design with Nios II Processor and VHDL Examples
- Embedded SoPC Design with Nios II Processor and Verilog Examples
- by Chi-Ying TSUI, Ph.D (The Hong Kong University of Science and Technology, HKUST - Department of Electronic & Computer Engineering)
- Lecture notes
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