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Compiler settings are a group of settings used by the Compiler to specify a design entity as the compilation focus, the type of compilation you want to perform, the device family and device you want to use, and other options. You apply these settings when compiling any design in a project.
When you create a new project, the Quartus® II software creates default Compiler settings that have the same name as the project's initial top-level design entity, and uses these default Compiler settings as the current Compiler settings. You can also specify and save your own customized Compiler settings for a project in the pages under the Compiler Settings page of the Settings dialog box (Assignments menu), as described in the following topics:
To create new groups of Compiler settings, refer to Creating New Compiler Settings.
To delete one or more groups of Compiler settings from the project, refer to Deleting Compiler Settings.
To specify the current Compiler settings to use for a compilation, refer to Specifying the Current Compiler Settings.
To set the compilation focus for the current Compiler settings, refer to Setting the Compilation Focus.
To specify the device family for the device you want to target for compilation, whether to use a specific device or automatic device selection, the devices available for device selection, and the specific target device (if applicable), refer to Specifying the Device Family & Device for Compilation.
To specify general device options for the target device, refer to Specifying General Device Options.
To specify the configuration scheme for the target device and the options available with that scheme, refer to Specifying Configuration Scheme Options.
To direct the Compiler to generate optional programming files for the target device, refer to Generating Optional Programming Files for SRAM Object Files and Generating Optional Programming Files for Programmer Object Files.
To specify a specific use for all unused pins on the target device, refer to Reserving All Unused Pins in a Device.
To specify the I/O standard for the target device, refer to Specifying the I/O Standard for a Device.
To specify pin assignments for the target device, refer to Assigning Pins.
To specify dual-port RAM signal routing paths for ARM-Based Excalibur™ devices, refer to Specifying Routing Paths for ARM-Based Excalibur Dual-Port RAM Signals.
To specify bridge, interrupt, and embedded processor core debug extension routing paths for EPXA4 or EPXA10 devices, refer to Specifying Routing Paths for ARM-Based Excalibur Bridges, Interrupts, and Debug Extensions.
To specify migration devices for an ACEX® 1K, APEX™ II, APEX™ 20K, FLEX 10KE, MAX® 3000, MAX 7000, or Stratix™ device, refer to Specifying Devices for Device Migration.
To specify options that control the compilation speed and the amount of disk space used for compilation, and to automatically route SignalProbe™ signals during compilation, modify the latest fitting results during a SignalProbe compilation, and use back-annotated routing constraints during compilation, refer to Specifying Compiler Mode Settings.
To specify the type of timing-driven compilation, if any, you want to use, refer to Specifying Compiler Settings for Timing-Driven Compilation.
To specify settings for incremental synthesis, refer to Saving Synthesis Results for an Entity to a Verilog Quartus® Mapping File.
To use the fast fit feature to increase compilation speed by up to 50%, refer to Increasing Compilation Speed with the Fast Fit Feature.
To specify the starting value you want the Fitter to use when determining the initial placement of a design, refer to Specifying the Starting Value for the Initial Placement of a Design.
To specify whether the Fitter performs final placement optimizations, refer to Performing Final Placement Optimizations.
To use the SignalProbe feature to route user-specified signals without having to do a full compilation, refer to Performing a SignalProbe Compilation on a Design.
To specify options for the Design Assistant, refer to Analyzing Designs with the Design Assistant.
To specify options for optimizing netlists during synthesis and fitting, refer to Optimizing Netlists During Synthesis & Fitting.
You can also use the Compiler Settings wizard (Assignments menu) to specify many of the Compiler settings that are in the Compiler Settings page.
To associate the current Compiler settings with the currently selected design file in the Quartus II software, without using the Compiler Settings page or the Compiler Settings wizard, use the Set Compiler Focus to Current Entity or Add Current Entity at Top Level command (Project menu).
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