Quartus

Verilog HDL Case Statement warning: implemented Verilog HDL parallel_case directive at <location> -- differences between design synthesis and simulation may occur

CAUSE: At the specified location in a Verilog Design File (.v), you used the parallel_case directive in a Case Statement that does not contain mutually exclusive case item expressions. The parallel_case directive directs the Logic Synthesizer to implement parallel logic rather than a priority scheme for all case item expressions in the Case Statement. The Logic Synthesizer implemented the parallel_case directive; however, in doing so, the Logic Synthesizer may have created synthesized logic for the current design with functionality that differs from the functionality you simulated for the design.
ACTION: Check the synthesized logic for design integrity.

See also:

parallel_case language directive
Verilog HDL Language Directives

- PLDWorld -

 
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