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Conditional Signal Assignment Statements list a series of expressions that are assigned to a target signal after the positive evaluation of one or more Boolean expressions. The following example shows a basic 2-to-1 multiplexer in which the value input0 is assigned to output when sel equals '0'; otherwise, the value input1 is assigned to output.

ENTITY condsig IS
   PORT
   (
      input0, input1, sel   : IN STD_LOGIC;
      output                : OUT STD_LOGIC
   );
END condsig;

ARCHITECTURE maxpld OF condsig IS
BEGIN

   output <= input0 WHEN sel = '0' ELSE input1;
      
END maxpld;

When a Conditional Signal Assignment Statement is executed, each Boolean expression is tested in the order in which it is written. The value of the expression preceding a WHEN keyword is assigned to the target signal for the first Boolean expression that is evaluated as true. If none of the Boolean expressions are true, the expression following the last ELSE keyword is assigned to the target. The following Conditional Signal Assignment Statement has multiple alternatives.

ENTITY condsigm IS
   PORT
   (
      high, mid, low    : IN STD_LOGIC;
      q                 : OUT INTEGER
   );
END condsigm;

ARCHITECTURE maxpld OF condsigm IS
BEGIN

q <= 3 WHEN high = '1' ELSE       -- when high
     2 WHEN mid  = '1' ELSE       -- when mid but not high
     1 WHEN low  = '1' ELSE       -- when low but not mid or high
     0;                           -- when not low, mid, or high

END maxpld;

In this example:

• 3 is assigned to q when high is '1'
• 2 is assigned to q when mid is '1' but high is not '1'
• 1 is assigned to q when low is '1' but high and mid are not '1'
• 0 is assigned to q when high, mid, or low do not equal '1'

For more information, see the following sections of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual:

• Section 9.5: Concurrent Signal Assignment statements
• Section 9.5.1: Conditional Signal Assignments

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