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The simple Signal Assignment Statements shown in the following example create an AND gate and connect two nodes, respectively. These statements are executed concurrently.

ENTITY simpsig IS
   PORT
   (
      a, b, e    : IN STD_LOGIC;
      c, d       : OUT STD_LOGIC
   );
END simpsig;

ARCHITECTURE maxpld OF simpsig IS
BEGIN

   c <= a AND b;   -- creates an AND gate
   d <= e;         -- connects two nodes

END maxpld;

In this example, the signal c receives the value of a AND b, and the signal d receives the value of e.

For more information, see "Section 9.5: Concurrent Signal Assignment Statements" in the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual.

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