In Xilinx FPGAs, each CLB contains 2 flip-flops which often go unused. Using such a flip-flop does not use any extra resources in most cases, as it will be located in the block which computes the result.
Latches have to be built using CLB function generators and require 1 CLB per bit (whereas a flip-flop normally comes for free).
Sometimes, of course, the exact functionality of either a flip-flop or a latch is required. In these cases, the appropriate type of storage element has to be used. But when the exact nature of the storage element is of minor importance, flip-flops are obviously beneficial.
The VHDL description methods for latches and flip-flops can be found in figures 6 and 5, respectively.
Figure 5: VHDL description for flip-flop.
Figure 6: VHDL description for latch.