4
VHDL signals, signal assignments, signal attributes and resolution functions

prepared by P. Bakowski

Introduction

In  previous chapters we introduced and discussed two object classes used to describe the sequences of operations: the variables and the constants. The hardware behavior is in large extent parallel. It means that hardware operations or components are active independently.  They communicate through interconnections carrying the signals. That is why VHDL includes the objects called signals. Signals are objects whose values may be changed and have time dimension.
The essential signal related operation is signal assignment.

Contents: signal and signal assignments, signal and variable, inertial delay, transport delay, signal attributes , resolution functions, signals versus variables,  exercises
 

VHDL signal and signal assignment

Signals values are changed by signal assignment statements. The simplest form of a signal assignment is:
signal_name <= value;  -- assigned after delta delay
This expression assigns the value of the signal at the beginning of the next simulation cycle. The left hand side of the signal assignment is referred to as target. When no explicit delay time is provided, the default time is a delay called delta delay.

The target signal may be assigned an explicit delay:

signal_name <= value after time_expression; -- called inertial delay
signal_name <= reject value after time_expression; -- called reject inertial delay
or
signal_name <= transport value after time_expression; -- called transport delay
signal res, sa, sb : integer;
signal a,b : bit;
a <=  b after 10 ns;
a <= transport b after 10 ns;
res <= sa + sb ;
Each signal has associated with it a projected output waveform. This output waveform  is represented by a list of transactions giving future values for the signal. The mechanism maintaining the state of the list of transactions is  referred to as signal driver. A signal assignment adds transactions to this signal driver.

For example, the simple signal assignment:

a <=  not b after 10 ns;
will add a new element to the signal driver and cause the signal a to assume the value not b 10 ns after the assignment is performed.

It is possible to apply  multiple transactions in one signal assignment. In this case the delay times  must be specified in ascending order.

type mlsig is ('0', '1', 'Z');
signal onde: mlsig:='0';
onde <= '1' after 5 ns, 'Z'after 10 ns, '1' after 15 ns, '0' after 20 ns;
..

Selected signal assignment

Selected signal assignment represents an action in which the signal target is assigned the value chosen from a list of provided assignments.
 
with op_code select
sortie <= a and b after 6 ns when "001";
sortie <= a or b after 5 ns when "010";
sortie <= a nor b after 4 ns when "011";
sortie <= a xor b after 7 ns when "100";
sortie <= a nand b after 4 ns when "101";
sortie <= a when others;
Note that the selected signal assignments corresponds to a case .. with...with .. process statement.
 

Delays

The hardware operate in a physical space where the execution of all activities or operations require some interval of time. In case of VHDL these intervals are called delays. A delay separates the beginning of an action from its end. Different physical phenomena imply different kinds of delays. Practically we can discern two kind of delays: inertial delay and propagation delay.

inertial delay

VHDL provides two different models of time delay:

 
An inertial delay is treated as default delay model and is specified by omitting the word transport from the signal assignment. The inertial delay is used to model devices which do not respond to input pulses shorter than their output delay. For example, the impulse to be absorbed by RC time-constant relative to the given signal input.
 

The following are the actions performed by the simulator when  an inertial delay transaction is added to a driver.

 
The following is an example of signal driver (sig) seen at time 0 ns is:
 
20 ns 30 ns 40 ns 60 ns
'1' '0' '1' 'Z'
and the assignment:
sig <= '1' after 50 ns;
The resulting output waveform is :
 
40 ns 50 ns
'1' '1'
 

Remember that the inertial delay deletes all transient impulses which are shorter than the proposed delay. Suppose a signal sin carrying a transient impulse '0' => '1' => '0' with '1' lasting 3 ns; and following signal assignment:

sout <= sin after 10 ns;
The application of the transient will not be seen at sout signal.
 
Remark:  When a multiple transaction is specified with inertial delay, only the first element of transaction uses inertial delay; the rest are treated as being transport delay transactions.

reject inertial delay

In order to model the inertial delays more precisely, in VHDL'93 a new inertial delay mode is introduced: inertial delay with pulse rejection window.
Example:
out_sig <= reject 5 ns inertial not in_sig a after 15 ns;
The above assignment models an inverter which has a delay of 15 nanoseconds but absorbs all  input signal changes that persist less than 5 nanoseconds.

transport delay

The second kind of the delay provided by VHDL is transport delay. This kind of delay is useful to model transit delays. For example the integrality of an input signal carried by an ideal transmission line is received at its output.
The transport delay removes the requirement that inputs persist at least for the delay time. Transient impulses are not suppressed; any change on the inputs may change the output signal state, no matter how short is the input impulse.
In the signal driver all old transactions scheduled to occur after the first new transaction are deleted before the new transactions are added. The new transport transactions supersede the old ones.
The following is an example of signal driver (sig) seen at time 0 ns (actual state '0') is:
 
30 ns 50 ns 70 ns
'1' 'Z' '0'
After the execution of the assignment at time 15 ns (actual state '0'), :
sig <= transport `Z' after 40 ns;
the state of the driver would be ('Z' supersedes '0') :
 
15 ns 35 ns 40 ns
'1' 'Z' 'Z'
 

Inertial delay versus transport delay

The following examples show the output waveform in response to an input waveform entree using inertial assignment (a <= ..) and transport assignment  (b <= .. ).  In the first case , the inertial delay is probably the right choice because we wish to absorb transient perturbation.

In the second case, when we are going to model serial transmission line, the transport delay is more appropriate because the output waveform must mimic the input waveform exactly, regardless of the delay.

signal-related attributes

The signals are feature rich objects. As they evolve in time the designer my need to know their states in a given instance but also their past "behavior". The analysis of the signal driver allows to extract some signal related information considered as signal attributes.
There are two kind of signal related attributes:
signal entree: bit;
if entree'event and entree='1' then ... -- rising edge : entree'event has a boolean result
else ...

attribute 'delayed

An example of a complete description of horloge entity:
entity horloge is
generic(period:time:=25 ns);
port(ph0,ph1: out bit);
end horloge;
architecture use_attributes of horloge is
signal con: bit:='0';
begin
con <= not con after period;
ph0 <=con;
ph1 <= con'delayed(period/2);
end use_attributes;
 

attribute `stable

The `stable attribute is a boolean signal whose value is TRUE when an event has not occurred on the signal for the given time; otherwise is FALSE.

Detection of spikes (transients):

entity dff is
port(d: in bit; q : out bit);
end dff;
architecture spike_protected of dff is
begin
process
begin
wait until d'stable(5 ns);
q<= d after 7 ns;
end process;
end spike_protected;

attribute 'transaction

The `transaction attribute is a bit signal which toggles every time when a transaction has occurred on the signal. Note that the `transaction attribute produces events even if the value of the signal has not changed.
 

attributes 'active, 'event

The `active attribute is a boolean signal which is TRUE when a transaction has occurred on the signal during the current simulation cycle. The `event attribute is a boolean signal which is TRUE when an event has occurred on the signal during the current simulation cycle. The following excl_process is sensitive to two input signals but its behavior depends on whether or not each of the inputs has changed.

signal-related attributes (4) - 'last_active, 'last_event

The `last_active attribute returns the amount of time that has elapsed since there was a transaction on the signal. The `last_event attribute returns the amount of time that has elapsed since there was an event on the signal. The `last_value attribute returns the value of the signal before the last event.

Resolution function

The signals can have multiple drivers. The value of the signal is a function of all the drivers of that signal. The following figure shows an example of a bus signal which is driven by four independent signals. The value bus is computed by a bus resolution function (brf in this example).

The drivers are labeled s1,s2,s3, and s4. The value of the signal dbus is computed by a bus resolution function (brf in our example). Bus resolution functions are user-defined and are evaluated when one of the drivers of the signal receives a new value (event). The 'resolved' value is then generated by the bus resolution function.

Let us take a three-valued (tri-state) logic called TSL as follows and declare the bfr function;

type TSL is ('0','1','Z');
type TSL_V is array (integer range <>) of TSL;
The resolved by the bfr function signal is to be declared as follows:
signal dbus : bfr TSL;
More general way to declare a resolved signal is :
subtype res_tsl is bfr TSL;
signal dbus : res_tsl;
Now we can define a simple bus resolution function for this tristate logic:
function brf (signal ins: TSL_V) return TSL is
variable resolved_value: TSL:='Z';
begin
for i in ins'range loop
if ins(i) /= 'Z' then
resolved_value:= ins(i);
exit;
end if;
end loop;
return resolved_value;
end brf;
The function above just scans the input drivers in the ins vector of TSV type and selects the value of the first driver that is not equal to 'Z'. Here, the assumption is that only one driver is currently active (carries '1' or '0').  In general this assumption is to strong while in reality more than one signal may be active at the same moment. That is why we need a more complete resolution function able to detect the potential conflicts.
function brf_2 (signal ins: TSL_V) return TSL is
variable resolved_value: TSL:='Z';
variable etat: TSL:='Z';
begin
for i in ins'range loop
if ins(i) /= 'Z' then
assert (etat = 'Z')
report "second active driver"
severity warning;
resolved_value:= ins(i);
etat:= ins(i);
end if;
end loop;
return resolved_value;
end brf;
The following  example contains a simple package which defines a resolved data type (FSL) consisting of four possible values: '0', '1','X' and 'Z'.  This FSL_P package includes  four-state-logic type  type definition, an array type of FSL and the definition of resolution function. Note that the  resolution function is defined by using a resolution table and not an algorithm like in the example above.
package FSL_P is
type FSL is ('0','1','X','Z');
type FSL_V is array (natural range<>) of FSL;
function resolve_FSL (vect: FSL_V) return FSL;
subtype FSL_resolved is resolve_FSL FSL;  -- note that the resolved type is a subtype of FSL type
end FSL_P;
package body FSL_P is
type FSL_table is array(FSL,FSL) of FSL;
constant res_table: FSL_table:=
( -- 0   1   X   Z
   ('0','X','X','0'),  -- 0
   ('X','1','X','1'),  -- 1
   ('X','X','X','X'),  -- X
   ('0','1','X','Z')   -- Z
);
function resolve_FSL (vect: FSL_V) return FSL is
variable result:FSL;
begin
if (vect'length=1) then  -- if single signal driver ?
result:=vect(vect'low); -- then return its value
else
result:='Z';
for i in vect'range loop
result:=res_table(result,vect(i));
end loop;
end if;
return result;
end resolve_FSL
end FSL_P;
Remark:
All complete simulation environments provide standard logic package. This package defines resolution function used with std_logic signals

Comments on signal assignments versus variable assignments

The executable section of a process may contain several signal and variable assignments. These assignments are arranged and, in case of variable assignments are executed in a sequential (typographic) order. This sequential execution is also called procedural execution.

The variable assignments:

variable a,s,t: integer;
...
a := s + t;
b := a * r;
Note that the new value of a is calculated immediately and is used in the following assignment. If we rewrite the above expressions using signal objects, we obtain two independent processes (proc_1, proc_2).
signal a,s,t: integer;
...
b <= a * r; -- second process with sensitivity list of a and r (equivalent to)
a <= s + t; -- first process with sensitivity list of s and t (equivalent to)
If we assume that both s and r change at time t0; then both processes are activated simultaneously and the new values of a and b are evaluated concurrently at time t0+delta. delta represents one simulation cycle. It is infinitely small but greater than zero. After the evaluation of all assignments scheduled for the given simulation cycle, next simulation cycle starts after a delta time.

In our example the next value for signal a will be ready after a delta time. This in turn will activate the second process and generate a new value for signal b after a following delta time. Note that the order of execution of signal assignments is independent of their typographic order. This kind of execution is called non-procedural.
 

The following tables provide the comparison between variable and signal evaluations for a given example.
 
variables
t0-delta
t0
t0+delta
s
2
8
7
t
4
4
5
a
6
12
12
r
1
2
2
b
6
24
24
 
signals
t0-delta
t0 
t0+delta
t0+2*delta
s
2
8
7
7
t
4
4
5
5
a
?
6
12
12
r
1
2
2
2
b
?
?
12
24
 

Now we can consider an example of a simple rs flip-flop. The process below describes the operations of this flip-flop using two signal assignments.

rs_p: process(r,s)
begin
q <= r nand nq;
nq <= s nand q;
end process rs_p;
Question:

Is it possible to describe the function of the above rs flip-flop by using  variable assignments exclusively?

Exercises