prepared by P. Bakowski
Contents: signal and signal
assignments, signal and
variable, inertial delay, transport
delay, signal attributes , resolution
functions, signals versus
The target signal may be assigned an explicit delay:
For example, the simple signal assignment:
It is possible to apply multiple transactions in one signal assignment.
In this case the delay times must be specified in ascending order.
VHDL provides two different models of time delay:
The following are the actions performed by the simulator when
an inertial delay transaction is added to a driver.
Remember that the inertial delay deletes all transient impulses which
are shorter than the proposed delay. Suppose a signal sin
carrying a transient impulse '0' => '1' => '0'
with '1' lasting 3 ns; and following signal assignment:
In the second case, when we are going to model serial transmission line,
the transport delay is more appropriate because the output waveform must
mimic the input waveform exactly, regardless of the delay.
Detection of spikes (transients):
of buffer is
of sh_reg is
The drivers are labeled s1,s2,s3, and
s4. The value of the signal dbus
is computed by a bus resolution function (brf in our example).
Bus resolution functions are user-defined and are evaluated when one of
the drivers of the signal receives a new value (event). The 'resolved'
value is then generated by the bus resolution function.
Let us take a three-valued (tri-state) logic called
TSL as follows and declare the bfr function;
The variable assignments:
In our example the next value for signal a will be ready
after a delta time. This in turn will activate the second
process and generate a new value for signal b after a following
delta time. Note that the order of execution of signal assignments
is independent of their typographic order. This kind of execution is called
Now we can consider an example of a simple rs flip-flop. The process
below describes the operations of this flip-flop using two signal assignments.
Is it possible to describe the function of the above rs flip-flop
by using variable assignments exclusively?