Pins of the XC4000E and the XC4000XL devices in a 84 PLCC package

and associated connections on
the Xilinx FPGA Demoboard and the XESS XS40 Board




The following table lists the pins numbers and names for the 84 pin XC4000 FPGA. For the FPGA demoboard, the pins are connected to headers surrounding the socket on the demoboard. The numbers on the demoboard headers increase from the inside row to the outside, counter-clockwise. The corners at each header give the starting numbers. For a description of the FPGA Demoboard or the XS40 board see the EE FPGA page.

After configuration, any input pin that is not used will be configured as an input with a 50-100 kOhm pull-up resistor. Used input pins will also be connected to a pull-up resistor of the same value. This is done in the IOB block on the FPGA device. For more information about the XC4000 FPGA device, please consult the Xilinx website.

The pin numbering of the 84 pin FPGA is given in the following figure.
 

FPGA Demoboard
SPECS XC4000

Device : XC4005XL and XC4010E

Power supply (XL device Vcc=3.3V and E device Vcc=5V)

No. of System Gates: 3-10K and 7-20K

No. Logic Cells: 466 and 950

Max RAM bits: 6,272 and 12,800

fsystem freq: 96 MHz

Outputs: tri-state,  can drive 12mA or 24mA (see data book for more information)
XS40 Board

Figure 1: Pin numbering of the 84 pin PLCC

Table I: Pin numbers of the 84-pin FPGA and corresponding pins on the demo- and XS40 boards

CHIP PIN No.
Name
FPGA DEMO-BOARD 
Pin nmbers and Comments

XS40 board connection
1
 GND Ground
2
 VCC (5V for E, 3.3V for  XL) Power supply (5V for XC4000E)  pin 2 of the board is connected to 5V (pin 54 of the board is connected to 3.3V))
3
 I/O (A8) General I/O  A0 (Address bit of the SRAM)
4
 I/O (A9) General I/O  A1 (SRAM)
5
 I/0 (A10) General I/O A2 (SRAM)
6
 I/O (A11) General I/O P1.3 (Port 1.3 of the microcontroller)
7
 I/O (A12) General I/O  P1.0
8
 I/O (A13) General I/O  P1.1
9
 I/O (A14) General I/O  P1.2
10
 SGCK(A15,I/O) General I/O  P0.7(AD7).D7 (multiplexed address/data port P0.7 and also conntected to data pin D7 of SRAM
11
 VCC Vcc
12
 GND GND
13
 PGCK1(A16,I/O) [1] Clock of external oscillator (Y1) (not on all boards available); can also used as I/O  CLK (from Programmable oscillator)
14
 I/O(A17) PSEN (program store enable)
15
 I/O(TDI) XChecker TDI (Test data in) (for boundary scan, can be reused).
16
 I/O(TCK) XChecker TCK (Test clock ) (for boundary scan, can be reused). A16 (address bit A16 of the SRAM - only on the 128 KB version)
17
 I/O(TMS) XChecker TMS (test mode) (for boundary scan, can be reused).
18
 I/O 7-segment disp.-f (S5)/ Red1of VGA
19
 I/O SW3 -1 (gen. purpose switch) 7-segment disp.-a (S6)/Hor SYNC of VGA
20
 I/O SW3 -2 7-segment disp.-g (S3)/ Green1of VGA
21
 GND
22
 VCC
23
 I/O SW3 -3 7-segment disp.-b (S4)/ Red0 of VGA
24
 I/O SW3 -4 7-segment disp.-e (S2)/ Green0 of VGA
25
 I/O SW3 -5 7-segment disp.-d (S0)/Blue0  of VGA
26
 I/O SW3 -6 7-segment disp.-c (S1)/ Blue1 of VGA
27
 I/O SW3 -7 P3.7(/RD)
28
 I/O SW3 -8 P2.7( A15): Port P2.7 of microcontroller and addr. bit A15 of SRAM (only on the 128KB)
29
 SGCK2(I/O) [2] 7-segment disp. U7-e ALE (address latch enable pin)
30
 O(M1) XChecker RD/ readback, & SW2-5 ; 
31
 GND GND
32
 I(MO) XChecker RT/readback, & SW2-4 (Mode) Parallel port data output PC-D6 (pin 8 of the J1 connector)
33
 VCC Vcc
34
 I(M2) SW2-6 (multiple prgrm enable) Parallel port data output PC-D7 (pin 9 of the J1 connector)
35
 PGCK2(I/O) 7-segment disp. U7-d P0.4(AD4).D4
36
 I/O(HDC) 7-segment disp. U7-c; Hi untill configuration complete. Pin is available after configuring.  RST (reset input of the microconroller)
37
 I/O(/LDC) 7-segment disp. U7-dec. pt.; LO untill configuration complete; Pin is available after configuring.  Output clock generated by the FPGA, connected to the clock input XTAL1 of the microcontroller.
38
 I/O 7-segment disp. U7-b  P0.3(AD3).D3 (multiplexed address/data port and also conntected to data pin D3 of SRAM
39
 I/O 7-segment disp. U7-a, P0.2(AD2).D2
40
 I/O 7-segment disp. U7-f  P0.1(AD1).D1
41
 I/O(/INIT) 7-segment disp. U8-dec. pt.; XChecker INIT  P0.0(AD0).D0
42
 VCC Vcc
43
 GND GND
44
 I/O 7-segment disp. U7-g Parallel port data output PC-D0 (can be used for clock signals - has an inverting Schmitt-trigger); (pin 2 of the J1 connector)
45
 I/O 7-segment disp. U8-e Parallel port data output  PC-D1 (can be used for clock signals - has an inverting Schmitt-trigger) (pin 3 of the J1 connector)
46
 I/O 7-segment disp. U8-d Parallel port data output  PC-D2 (J1-4)
47
 I/O 7-segment disp. U8-c Parallel port data output PC-D3  (J1-5)
48
 I/O 7-segment disp. U8-b Parallel port data output PC-D4 (J1-6)
49
 I/O 7-segment disp. U8-a Parallel port data output PC-D5 (J1-7)
50
 I/O 7-segment disp. U8-f P2.4 of microcontroller and addr. bit A12 of SRAM
51
 SGCK3(I/O) 7-segment disp. U8-g P2.2 (A10)
52
 GND GND
53
 DONE XChecker DONE
54
 VCC 3.3V
55
 /PROGRAM XChecker PROG; also SW6 (Prog. switch)
56
 I/O(D7) SW2-7: when ON connects RST (SW4) pushbutton to pin 56 (reset to ground).  P2.3 (A11)
57
 PGCK3(I/O) LED D13 P2.1 (A9) (Port P2.1 of microcontroller and Addr bit A9 of SRAM
58
 I/O(D6) LED D14 P2.5 (A13)
59
 I/O(D5) LED D15 P2.0(A8).A8
60
 I/O(/CS0) LED D16 P2.6 (A14)
61
 I/O(D4) LED D9 /OE (SRAM output enable pin)
62
 I/O LED D10 P3.6(/WR), /WE (Port 3.6 of the microcontroller and /WE pin of the SRAM
63
 VCC Vcc
64
 GND GND
65
 I/O(D3) LED D11 /CE (SRAM chip enable)
66
 I/O(RS) LED D12 P1.6  and parallel port PC-S5
67
 I/O(D2) P1.7 and vertical sync VSYNC of the VGA 
68
 I/O P3.4(T0), PS/2 CLK
69
 I/O(D1) P3.1(TXD), PC-S6  and PS/2 data line
70
 I/O(/, RDY, /BUSY) P1.5 and parallel port PC-S3
71
 I/O(D0,DIN) XChecker: Data IN
72
 SGCK4(DOUT,I/O)
73
 CCLK XChecker CCLK pin
74
 VCC Vcc
75
 O, TDO not connected PC-S7 (status input pin of the PC parallel port)
76
 GND GND
77
 I/O(A0,/WS) General I/O  P1.4 and parallel port PC-S4
78
 I/O, PGCK4(A1) General I/O A3 (address bit of SRAM)
79
 I/O(CS1,A2) General I/O  A4 (SRAM)
80
 I/O(A3) General I/O  P0.6(AD6).D6
81
 I/O(A4) General I/O  P0.5(AD5).D5
82
 I/O(A5) General I/O  A5 (SRAM)
83
 I/O (A6) General I/O A6 (SRAM)
84
 I/O(A7) General I/O A7 (SRAM)

NOTES:

1. PGCK 1-4: are primary global inputs wich drive each a dedicated internal global net with short delays and minimal skew. If not used, each of these pins can be a user-programmable I/O. On the demobaord PGCK1 (pin 13) can be used for an external oscillator clock input.

2. SGCK1-4: These are four secondary global inputs.  If not used, each of these pins can be a user-programmable I/O.

Reference:

The Programmable Logic Data Book, Xilinx, San Jose, 1999. (http://www.xilinx.com/partinfo/databook.htm)
XS40, XSP Board V1.4 User Manual, XESS Corp, Apex, 1999 (http://www.xess.com/).


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Board description: FPGA Demoboard | XS40 | XS95 |
Pinouts: XC4000 | XC9500.

Created by Jan Van der Spiegel; August 30, 1997; updated June 12,  2000