Standard Delay Format (SDF) Timing Annotation

---

Chapter contents

Specifying SDF files for simulation

Instance specification

SDF specification with the GUI

Errors and warnings

VHDL VITAL SDF

SDF to VHDL generic matching

Resolving errors

Verilog SDF

The $sdf_annotate system task

SDF to Verilog construct matching

Optional edge specifications

Optional conditions

Rounded timing values

SDF for Mixed VHDL and Verilog Designs

Interconnect delays

Troubleshooting

Specifying the wrong instance

Mistaking a component or module name for an instance label

Forgetting to specify the instance

This chapter discusses ModelSim's implementation of SDF (Standard Delay Format) timing annotation. Included are sections on VITAL SDF and Verilog SDF, plus troubleshooting.

Verilog and VHDL VITAL timing data can be annotated from SDF files by using the simulator's built-in SDF annotator. ASIC and FPGA vendors usually provide tools that create SDF files for use with their cell libraries. Refer to your vendor's documentation for details on creating SDF files for your library. Many vendors also provide instructions on using their SDF files and libraries with ModelSim.

The SDF specification was originally created for Verilog designs, but it has also been adopted for VHDL VITAL designs. In general, the designer does not need to be familiar with the details of the SDF specification because the cell library provider has already supplied tools that create SDF files that match their libraries.

Note: In order to conserve disk space, ModelSim will read sdf files that were compressed using the standard unix/gnu file compression algorithm. The filename must end with the suffix ".Z" for the decompress to work.

Model Technology Incorporated Voice: (503) 641-1340 Fax: (503)526-5410 www.model.com sales@model.com