See Also

VHDL Design Files (.vhd) can be combined with other VHDL Design Files, Verilog Design Files (.v), Text Design Files (.tdf), Block Design Files (.bdf), and EDIF Input Files (.edf) into a hierarchical project. Lower-level files in a project hierarchy can be Altera-provided megafunctions, or user-defined megafunctions or macrofunctions.

The Quartus^® II software provides primitives and bus and architecture-optimized megafunctions. You can use Component Instantiation Statements to insert instances of any supported logic function. You can also use Register Inferences to implement registers. Precompiled design libraries are available for all Quartus II logic functions supported in VHDL.

If a VHDL Design File contains non-Quartus II function(s) that need to be mapped to Quartus II functions, you must use the VHDL Input page of the Settings dialog box (Assignments menu) to specify a Library Mapping File (.lmf) for the file.

This section includes the following topics:

• Using a Quartus II Logic Function
• Using a User-Defined Megafunction or Macrofunction
• Using Parameterized Functions & Generics
• Implementing CAM, RAM & ROM
• Implementing Inferred RAM

Back to Top