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In VHDL, you can create and use parameterized functions, including library of parameterized modules (LPM) functions supported by the Quartus^® II software.

To create a parameterized logic function in VHDL, the logic function's Entity Declaration must include a Generic Clause that lists all parameters (or "generics") used in the logic function and their optional default values.

You can instantiate a parameterized function with a Component Instantiation Statement in the same way as unparameterized functions, as described in Using a Quartus II Logic Function and Implementing a User-Defined Macrofunction or Megafunction, with a few additional steps:

• The logic function instance must include a Generic Map Aspect that lists all required parameters and any optional parameters for the instance. The Generic Map Aspect is based on the Generic Clause in the function's Component Declaration. For a VHDL-based function, the Generic Map Aspect in the Component Declaration is identical to the Generic Map in the function's Entity Declaration; for an AHDL-based function, it is based on the AHDL Function Prototype for the function; and for a Block Design File (.bdf)-based function, it is based on the PARAM primitives in the BDF.

  The help topic describing an Altera-provided parameterized function shows the Component Declaration for that function.

  You also assign values to parameters in the Generic Map Aspect of the logic function instance. If no value is specified for a parameter, the Compiler searches for a default value as described in Parameter Value Search Order.

• Because parameterized functions do not necessarily have default values for unconnected inputs, you must ensure that all required ports are connected.

The following example shows reg24lpm.vhd, a VHDL Design File (.vhd) for a 24-bit register that has an Entity Declaration and an Architecture Body that use two Altera-provided parameterized lpm_ff megafunctions. The Generic Map Aspect for each instance of lpm_ff defines the register width as 12 bits by setting the LPM_WIDTH parameter value to 12.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY lpm;
USE lpm.lpm_components.ALL;

ENTITY reg24lpm IS
   PORT(
      d      : IN  STD_LOGIC_VECTOR(23 DOWNTO 0);
      clk    : IN  STD_LOGIC;
      q      : OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END reg24lpm;

ARCHITECTURE a OF reg24lpm IS
BEGIN
   reg12a   : lpm_ff
      GENERIC MAP (LPM_WIDTH => 12)
      PORT MAP (data => d(11 DOWNTO 0), clock => clk, 
         q => q(11 DOWNTO 0));
   reg12b   : lpm_ff
      GENERIC MAP (LPM_WIDTH => 12)
      PORT MAP (data => d(23 DOWNTO 12), clock => clk, 
         q => q(23 DOWNTO 12));
END a;

The following VHDL Design File, reggen.vhd, contains the Entity Declaration and Architecture Body for reggen, a parameterized register function. The Generic Clause defines the REG_WIDTH parameter.

ENTITY reggen IS
   GENERIC(
      REG_WIDTH : INTEGER);
   PORT(
      d      : IN STD_LOGIC_VECTOR(REG_WIDTH - 1 DOWNTO 0);
      clk    : IN STD_LOGIC;
      q      : OUT STD_LOGIC_VECTOR(REG_WIDTH - 1 DOWNTO 0));
END reggen;

ARCHITECTURE a OF reggen IS
BEGIN
   PROCESS
   BEGIN
      WAIT UNTIL clk = '1';
      q <= d;
   END PROCESS;
END a;

The following VHDL Design File, reg24gen.vhd, instantiates two copies of reggen: reg12a and reg12b. The Package Declaration specifies the value of the TOP_WIDTH constant as the integer 24, and the HALF_WIDTH constant as the integer that is half of TOP_WIDTH. In the Generic Map Aspect of each instance of reggen, the constant HALF_WIDTH is explicitly assigned as the value of the REG_WIDTH parameter, thereby creating two 12-bit registers.

PACKAGE reg24gen_package IS
   CONSTANT TOP_WIDTH : INTEGER := 24;
   CONSTANT HALF_WIDTH : INTEGER := TOP_WIDTH / 2;
END reg24gen_package;

USE work.reg24gen_package.ALL;

ENTITY reg24gen IS
   PORT(
      d      : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
      clk    : IN STD_LOGIC;
      q      : OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END reg24gen;

ARCHITECTURE a OF reg24gen IS

   COMPONENT reggen
      GENERIC(
         REG_WIDTH : INTEGER);
      PORT(
         d      : IN STD_LOGIC_VECTOR(REG_WIDTH - 1 DOWNTO 0);
         clk    : IN STD_LOGIC;
         q      : OUT STD_LOGIC_VECTOR(REG_WIDTH - 1 DOWNTO 0));
   END COMPONENT;

BEGIN
   reg12a : reggen
      GENERIC MAP (REG_WIDTH => HALF_WIDTH)
      PORT MAP (d => d(HALF_WIDTH - 1 DOWNTO 0), clk => clk, 
      q => q(HALF_WIDTH - 1 DOWNTO  0));
   reg12b : reggen
      GENERIC MAP (REG_WIDTH => HALF_WIDTH)
      PORT MAP (d => d(HALF_WIDTH*2 - 1 DOWNTO HALF_WIDTH), clk => clk, 
      q => q(HALF_WIDTH * 2 - 1 DOWNTO HALF_WIDTH));
END a;

In functions with multiple parameters, parameter values can also be assigned with positional association in a Generic Map Aspect. The order of parameter values must be given in the same order as the parameters in the Generic Clause of the function's Component Declaration.

For more information, see "Section 9.6: Component Instantiation Statement" in the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual.

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