See Also

In VHDL, you can use a Component Instantiation Statement to create an instance of a Quartus^® II logic function. The Component Instantiation Statement also connects logic function ports to signals or interface ports of the associated entity/architecture pair. The ports of logic functions are defined with Component Declarations elsewhere in the file or in referenced packages.

VHDL does not directly support logic functions or ports with names that are VHDL keywords or that begin with a number. To use one of these names, you must enclose it in \ delimiters. For example, to use a user-defined function called package, you must specify \package\ in the Component Instantiation Statement. The Quartus II software automatically removes the \ delimiters of any logic function or port name during processing. The \ delimiters are also omitted from the Report window, HTML-Format Report File (.htm), and Text-Format Report File (.rpt) generated during compilation. Registers can also be implemented with Register Inferences. See Implementing Registers for more information. Additional requirements for using parameterized functions (such as library of parameterized modules [LPM] functions), are described in Using Parameterized Functions & Generics.

In the following example, a Component Instantiation Statement is used to create an instance of a DFF primitive and a TRI primitive.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

LIBRARY altera;
USE altera.maxplus2.ALL;

ENTITY compinst IS
   PORT
   (
      data, clock, clearn, presetn    : IN STD_LOGIC;
      q_out                           : OUT STD_LOGIC;
      a, b                            : IN STD_LOGIC;
      t_out                           : OUT STD_LOGIC
   );
END compinst;

ARCHITECTURE a OF compinst IS

BEGIN

   dff1 : DFF PORT MAP (d =>data, q => q_out, clk => clock, clrn =>
   clearn, prn => presetn);

   tri1 : TRI PORT MAP (a, b, t_out);

   
END a;

In this example, the library altera is declared as the resource library. The Use Clause specifies the maxplus2 package contained in the altera library.

A single instance of the DFF primitive is created with a Component Instantiation Statement. The values described in the Port Map Clause for each instance are mapped to the corresponding ports in the Component Declaration for the DFF primitive in the maxplus2 package. The ports of the dff1 primitive instance are connected by name, that is, ports are mapped directly to signals regardless of the order in which they are listed. The d port of the dff primitive is mapped to data, q to q_out, clk to clock, clrn to clearn, and prn to presetn.

A Component Instantiation Statement is also used to create a single instance of the TRI primitive. The ports in the tri1 primitive instance are associated by position: the first port (in) in the TRI primitive is mapped to a, the second port (oe) to b, and the third port (out) to t_out.

If, in a VHDL Design File (.vhd), you create one or more instances of a Quartus II VHDL primitive that has a Component Declaration in the maxplus2 package (which is in the \quartus\libraries\vhdlnn\altera directory, where nn is "87" or "93"), you must specify maxplus2.lmf as the Library Mapping File (.lmf) for the VHDL Design File. The Help topic describing an Altera-provided function shows the Component Declaration for that function.

For more information, see "Section 9.6: Component Instantiation Statement" in the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual.

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