See Also

You create a user-defined megafunction or macrofunction in VHDL using a Component Declaration, which specifies the ports of the function. You can use the Component Declaration in one of the following locations:

• In a Package Declaration at the beginning of the VHDL Design File (.vhd) that instantiates the function. The Package Declaration can contain the Component Declarations for all the functions that are instantiated in the VHDL Design File. This method of using Component Declarations is described here.

• In a Package Declaration in a separate VHDL Design File. This VHDL Design File must be in the project that uses the package. Also, the Package Declaration can contain any number of Component Declarations, and the VHDL Design File can contain any number of Package Declarations.

• In the architecture where the logic function is instantiated.

The Quartus® II software automatically specifies the current project directory as the work library. Therefore, the Compiler considers any packages it creates from a project's VHDL Design Files to be in the work library.

After you create the package for a user-defined function (or you implement a Component Declaration in the architecture where the function is to be instantiated), you can instantiate the function in a VHDL Design File with a Component Instantiation Statement, as described in Using a Quartus II Logic Function. If you are using a package, you must also identify the package with a Use Clause, and identify the design library that contains the package with a Library Clause.

Because the work library is the default library, you do not need a Library Clause to specify the work library; however, Altera® recommends that a VHDL Design File contain one Library Clause for each Use Clause. If a VHDL Design File contains non-Quartus II function(s) that need to be mapped to Quartus II functions, you must use the VHDL Input page of the Settings dialog box (Assignments menu) to specify a Library Mapping File (.lmf) for the file. For information on using parameterized macrofunctions and megafunctions, such as library of parameterized modules (LPM) functions, see Using Parameterized Functions & Generics.

The following example shows reg12.vhd, a VHDL Design File for a 12-bit register. This register has an Entity Declaration and an Architecture Body for the user-defined macrofunction reg12.

ENTITY reg12 IS
   PORT(
      d      : IN  STD_LOGIC_VECTOR(11 DOWNTO 0);
      clk    : IN  STD_LOGIC;
      q      : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
END reg12;

ARCHITECTURE a OF reg12 IS
BEGIN
   PROCESS
   BEGIN
      WAIT UNTIL clk = '1';
      q <= d;
   END PROCESS;
END a;

The following example shows reg24.vhd, a VHDL Design File that declares the reg24_package. The Package Declaration contains the Component Declaration for the reg12 function, as defined by reg12.vhd. The VHDL Design File then identifies the work library with a Library Clause, identifies the reg24_package package with a Use Clause, and instantiates the reg12 function with a Component Instantiation Statement.

PACKAGE reg24_package IS
   COMPONENT reg12
      PORT(
         d      : IN   STD_LOGIC_VECTOR(11 DOWNTO 0);
         clk    : IN   STD_LOGIC;
         q      : OUT   STD_LOGIC_VECTOR(11 DOWNTO 0));
   END COMPONENT;
END reg24_package;

LIBRARY work;
USE work.reg24_package.ALL;

ENTITY reg24 IS
   PORT(
      d      : IN  STD_LOGIC_VECTOR(23 DOWNTO 0);
      clk    : IN  STD_LOGIC;
      q      : OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END reg24;

ARCHITECTURE a OF reg24 IS
BEGIN
   reg12a   : reg12 PORT MAP (d => d(11 DOWNTO 0), clk => clk, 
           q => q(11 DOWNTO 0));
   reg12b   : reg12 PORT MAP (d => d(23 DOWNTO 12), clk => clk, 
           q => q(23 DOWNTO 12));
END a;

In this example, the ports for reg12 are listed in a Component Declaration in the reg24_package at the beginning of the file. The Architecture Body for reg24 contains two instances of reg12. Because the Component Declaration for the function is implemented in the Package Declaration, the VHDL Input File does not require a Component Declaration in the architecture that instantiates the function.

For more information, see the following sections of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual:

• Section 4.5: Component Declarations
• Section 9.6: Component Instantiation Statement

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