An Introduction to the Concepts of Timing and Delays in Verilog

Delays

Gate level modelling

module multiplexor_2_to_1(out, cnt, a, b);

   /*
    *  A 2-1 1-bit multiplexor
    */
   
   output out;
   input  cnt, a, b;
   wire	  not_cnt, a0_out, a1_out;
   
   not # 2    n0(not_cnt, cnt);        /* Rise=2, Fall=2, Turn-Off=2 */
   and #(2,3) a0(a0_out, a, not_cnt);  /* Rise=2, Fall=3, Turn-Off=2 */
   and #(2,3) a1(a1_out, b, cnt);  
   or  #(3,2) o0(out, a0_out, a1_out); /* Rise=3, Fall=2, Turn-Off=2 */
   
endmodule /* multiplexor_2_to_1 */
    

Dataflow modelling

Net Declaration Delay

The delay to be attributed to a net can be associated when the net is declared. Thereafter any changes of the signals being assigned to the net will only be propagated after the specified delay.

e.g. wire #10 out; assign out = in1 & in2;

If either of the values of in1 or in2 should happen to change before the assigment to out has taken place, then the assignment will not be carried out, as input pulses shorter than the specified delay are filtered out. This is known as inertial delay.

Regular Assignment Delay

This is used to introduce a delay onto a net that has already been declared.

e.g. wire out; assign #10 out = in1 & in2;

This has a similar effect to the code above, computing the value of in1 & in2 at the time that the assign statement is executed, and then storing that value for the specified delay (in this case 10 time units), before assigning it to the net out.

Implicit Continuous Assigment

Since a net can be implicitly assigned a value at its declaration, it is possible to introduce a delay then, before that assignment takes place.

e.g. wire #10 out = in1 & in2;

It should be easy to see that this is effectively a combination of the above two types of delay, rolled into one.

Behavioural modelling

Regular Delay Control

This is the most common delay used - sometimes also referred to as inter-assignment delay control.

e.g. #10 q = x + y;

It simply waits for the appropriate number of timesteps before executing the command.

Intra-Assignment Delay Control

With this kind of delay, the value of x + y is stored at the time that the assignment is executed, but this value is not assigned to q until after the delay period, regardless of whether or not x or y have changed during that time.

e.g. q = #10 x + y;

This is similar to the delays used in dataflow modelling.

Examples using delays

The Full-Adder

module full_adder(sum_out, carry_out, a, b, carry_in);
   
   /*
    * A gate-level model of a 1-bit full-adder
    */
   
   output carry_out, sum_out;
   input  carry_in, a, b;
   wire	  one_high, generate, propagate;
   
   xor #(3,2) x0(one_high, a, b);
   xor #(3,2) x1(sum_out, one_high, carry_in);
   and #(2,4) a0(generate, a, b);
   and #(2,4) a1(propagate, one_high, carry_in);
   or  #(3)   o0(carry_out, generate, propagate);
   
endmodule /* full_adder */
    

Full Adder : Output - no delays

Full Adder : Output - delays as specified

The Ripple Carry Adder

module ripple_carry_4_bit(sum_out, carry_out, a, b, carry_in);

   /*
    *  A gate-level model of a 4-bit ripple carry adder
    */

   output [3:0]	sum_out;
   output	carry_out;
   input [3:0]	a, b;
   input	carry_in;
   wire [2:0]	ripple;
		
   full_adder f_a0(sum_out[0], ripple[0], a[0], b[0], carry_in);
   full_adder f_a1(sum_out[1], ripple[1], a[1], b[1], ripple[0]);
   full_adder f_a2(sum_out[2], ripple[2], a[2], b[2], ripple[1]);
   full_adder f_a3(sum_out[3], carry_out, a[3], b[3], ripple[2]);

endmodule /* ripple_carry_4_bit */
    

4-bit Ripple Carry Adder : Output - no delays

4-bit Ripple Carry Adder : Output - delays as specified

The Carry Skip Adder

Blocking and Non-blocking Assignments

Blocking Assignments

Blocking assignments are the most basic of the assignment operations, and simply copy the value of the expression at the right hand side of the = operator to the variable on the left hand side. However, if two assignments that depend on each other are scheduled at the same time, e.g. an attempt to swap two variables, such as :

always @(posedge clk) a = b;

always @(posedge clk) b = a;

then a race condition occurs, and both a and b will end up with one of the values. The value that they are both left with will depend on which of the assignments was scheduled first.

Non-blocking Assignments

Non-blocking assignments eliminate the possibility of race conditions in situations like this, as at the time that the assignment operation is executed the expression on the right hand side of the <= operator is copied to an internal temporary variable, which is then copied to the variable on the left hand side. All of the `reads' for a particular timestep are carried out before any of the `writes', and so values can be safely swapped as below :

always @(posedge clk) a <= b;

always @(posedge clk) b <= a;

This time, the code has the intended effect.

module blocking;

   reg[7:0] a, b, c, d, e;

   
   initial begin
      $monitor($time, " :\ta = %d\t", a,
	       "b = %d\tc = %d\t", b, c,
	       "d = %d\te = %d", d, e);
      #50 $finish;
   end

   initial begin
         a = 2;
         b = 5;
      #1 a = c;
      #1 a = d;
      #2 a = 4;
      #2 a = 7;
         b = 6;
      #2 a = d;
      $display("a, b - done");
   end

   initial begin
         c = 1;
         d = c;
         e = a;
      #2 e = d;
         c = 0;      
         d = 3;
      #5 c = a;
         d = 1;
         d = 2;
      $display("c, d, e - done");
   end
    
endmodule /* blocking */
 	    

module non_blocking;

   reg[7:0] a, b, c, d, e;

   
   initial begin
      $monitor($time, " :\ta = %d\t", a,
	       "b = %d\tc = %d\t", b, c,
	       "d = %d\te = %d", d, e);
      #50 $finish;
   end

   initial begin
         a <= 2;
         b <= 5;
      #1 a <= c;
      #1 a <= d;
      #2 a <= 4;
      #2 a <= 7;
         b <= 6;
      #2 a <= d;
      $display("a, b - done");
   end

   initial begin
         c <= 1;
         d <= c;
         e <= a;
      #2 e <= d;
         c <= 0;      
         d <= 3;
      #5 c <= a;
         d <= 1;
         d <= 2;
      $display("c, d, e - done");
   end
    
endmodule /* non_blocking */
 	    

module blocking_intra;

   reg[7:0] a, b, c, d, e;

   
   initial begin
      $monitor($time, " :\ta = %d\t", a,
	       "b = %d\tc = %d\t", b, c,
	       "d = %d\te = %d", d, e);
      #50 $finish;
   end

   initial begin
      a = 2;
      b = 5;
      a = #1 c;
      a = #1 d;
      a = #2 4;
      a = #2 7;
      b = 6;
      a = #2 d;
      $display("a, b - done");
   end

   initial begin
      c = 1;
      d = c;
      e = a;
      e = #2 d;
      c = 0;      
      d = 3;
      c = #5 a;
      d = 1;
      d = 2;
      $display("c, d, e - done");
   end
    
endmodule /* blocking_intra */
 	    

module non_blocking_intra;

   reg[7:0] a, b, c, d, e;

   
   initial begin
      $monitor($time, " :\ta = %d\t", a,
	       "b = %d\tc = %d\t", b, c,
	       "d = %d\te = %d", d, e);
      #50 $finish;
   end

   initial begin
      a <= 2;
      b <= 5;
      a <= #1 c;
      a <= #1 d;
      a <= #2 4;
      a <= #2 7;
      b <= 6;
      a <= #2 d;
      $display("a, b - done");
   end

   initial begin
      c <= 1;
      d <= c;
      e <= a;
      e <= #2 d;
      c <= 0;      
      d <= 3;
      c <= #5 a;
      d <= 1;
      d <= 2;
      $display("c, d, e - done");
   end
    
endmodule /* non_blocking_intra */
 	    

Delay Models

Distributed Delay

The distributed delay method requires delays to be assigned to every element of the circuit - then the delay between any two points can be calculated by adding together the delays of the components through which the signal being monitored passes.

Lumped Delay

This is similar to the distributed delay approach, except that it is only modules (rather than their component parts) that are assigned delays. Normally, the delay assigned to the module is the longest path through it, to ensure that the model reflects the worst case performance.

Pin-to-pin Delay

(This technique is sometimes also referred to as the path delay method.) Delays are specified for each input to output pin pairing, rather than being associated with specific elements. This can be advantageous as it means that details of the internals of the module need not be known for the analysis to be carried out.

Pin to Pin Timing Specifications

specify
  (a => out) = 9;
  (b => out) = 7;
endspecify
	    

specify
  (a *> out) = 9;
endspecify
	    

specify
  specparam a_to_out = 9;

  (a => out) = a_to_out;
endspecify
	    

specify
  specparam a_high = 2;
  specparam a_low  = 4;

  if  (a) (a => out) = a_high;
  if (~a) (a => out) = a_low;
endspecify 
	    

Setup and Hold Times

Timescales

Setup and Hold Example

/****************************************************************************\
 *                                                                          *
 *                            The Towers of Hanoi                           *
 *                                                                          *
\****************************************************************************/

/*
 *  Setup up some global parameters, for ease of change.
 */

`define clk_period 20
`define setup_time 4
`define hold_time  1


/****************************************************************************\
 *                                                                          *
 *               'Basic building block' module definitions                  *
 *                                                                          *
\****************************************************************************/

module toggle(q, qbar, clk, toggle, reset);

   /*
    *  A mixed style model of a T-type (toggle) flip-flop,
    *  with a reset line and delays on the outputs.
    *  This first part is behavioural code.
    */

   output q, qbar;
   input  clk, toggle, reset;
   reg	  q;

   always @(posedge clk)
      if (reset == 1)
	 #5 q = 0;
      else if (toggle == 1)
	 #6 q = ~q;

   /*  This part is dataflow-style  */
   
   assign #1 qbar = ~q;

endmodule /* toggle */

module effr(q, clk, enable, reset, d);

   /*
    *  A behavioural model of an E-type (enable) flip-flop
    *  with a reset signal, and delays on the outputs.
    */

   output q;
   input  clk, enable, reset, d;
   reg	  q;

   /*
    *  This next block checks for timing violations of the 
    *  flip-flop's setup and hold times.
    */
   
   specify
      $setup(d, posedge clk, `setup_time);
      $hold(posedge clk, d, `hold_time);
   endspecify

   /*
    *  This is the actual code for the E-type.
    */
   
   always @(posedge clk)
      if (reset == 1)
	 #5 q = 0;
      else if (enable == 1)
	 #6 q = d;
   
endmodule /* effr */

module effs(q, clk, enable, set, d);

   /*
    *  Another behavioural model of an E-type, this time with
    *  a set line, and delays on the outputs.  The same timing
    *  checks as before are implemented here, too.
    */
   
   output q;
   input  clk, enable, set, d;
   reg	  q;
   
   specify
      $setup(d, posedge clk, `setup_time);
      $hold(posedge clk, d, `hold_time);
   endspecify
   
   always @(posedge clk)
      if (set == 1)
	 #5 q = 1;
      else if (enable == 1)
	 #6 q = d;
   
endmodule /* effs */



/****************************************************************************\
 *                                                                          *
 *    Now, the more complex modules for implementing the actual solution    *
 *                                                                          *
\****************************************************************************/

module evenSlice(bus, oneOut, zeroOut, clk, init, oneIn, zeroIn);

   /*
    *  A dataflow model of one bit slice of the full moves generator.
    *  The only differences between this module and the oddSlice one
    *  are in the initialisation values.  (Note the types of the
    *  flip-flops used.)
    */
   
   inout [3:0] bus;
   output      oneOut, zeroOut;
   input       clk, init, oneIn, zeroIn;
   
   wire	       enable, tq, tqbar;
   wire [1:0]  toPeg, fromPeg, new;
   
   toggle tog (tq, tqbar, clk, oneIn, init);
   effr   to0 (toPeg[0], clk, enable, init, new[0]);
   effs   to1 (toPeg[1], clk, enable, init, new[1]);
   effs from0 (fromPeg[0], clk, enable, init, toPeg[0]);
   effr from1 (fromPeg[1], clk, enable, init, toPeg[1]);

   assign #2 oneOut  =  oneIn & tq;
   assign #2 zeroOut = zeroIn & tqbar;
   assign #2 enable  = zeroIn & tq;
      
   assign #2 new[1] = ~(toPeg[1] & fromPeg[1]);
   assign #2 new[0] = ~(toPeg[0] & fromPeg[0]);
   
   assign bus = (enable == 1) ? {fromPeg, toPeg} : 4'bz;
   
endmodule /* evenSlice */

module oddSlice(bus, oneOut, zeroOut, clk, init, oneIn, zeroIn);

   /*
    *  See the comments for the evenSlice module.
    */
   
   inout [3:0] bus;
   output      oneOut, zeroOut;
   input       clk, init, oneIn, zeroIn;
   
   wire	       enable, tq, tqbar;
   wire [1:0]  toPeg, fromPeg, new;
   
   toggle tog (tq, tqbar, clk, oneIn, init);   
   effs   to0 (toPeg[0], clk, enable, init, new[0]);
   effs   to1 (toPeg[1], clk, enable, init, new[1]);
   effs from0 (fromPeg[0], clk, enable, init, toPeg[0]);
   effr from1 (fromPeg[1], clk, enable, init, toPeg[1]);

   assign #2 oneOut  =  oneIn & tq;
   assign #2 zeroOut = zeroIn & tqbar;
   assign #2 enable  = zeroIn & tq;
   
   assign #2 new[1] = ~(toPeg[1] & fromPeg[1]);
   assign #2 new[0] = ~(toPeg[0] & fromPeg[0]);
   
   assign bus = (enable == 1) ? {fromPeg, toPeg} : 4'bz;
   
endmodule /* evenSlice */

module start_button(go, clk, press);

   /*
    *  A gate level model of the start button, with the functionality
    *  as described elsewhere.
    */

   output  go;
   input   clk, press;
   wire	   e_out, not_press;
   supply1 vdd;

   /*
    *  This block checks that the pulse with on the input line is
    *  wider than 3, otherwise it is invalid.
    */
   
   specify
      specparam min_time = 3;
      $width(posedge press, min_time);
   endspecify
   
   effs       st_0 (e_out, clk, vdd, press, vdd);
   not #(1)    n_0 (not_press, press);
   and #(2,1)  a_0 (go, e_out, not_press);

endmodule /* start_button */
	   
module tower(from_peg, to_peg, done, clk, start);

   /*
    *  This is a dataflow model of the actual move generator - to 
    *  be thought of as a stack (or tower) of modules, each of which
    *  with one disk of the puzzle.
    * 
    *  It brings together all of the other modules, and presents a
    *  clean interface to the outside world, taking a 'start' signal
    *  and returning a 'done' signal, once the sequence has been 
    *  completed.
    */
   
   output [1:0]	from_peg, to_peg;
   output	done;	
   input	clk, start;
   wire [4:0]	oneOut, zeroOut;
   wire [3:0]	bus;
   wire		init;		
   supply1	vdd;

   start_button  st_0(init, clk, start);
   oddSlice  rung0 (bus, oneOut[0], zeroOut[0], clk, ~init, vdd, vdd);
   evenSlice rung1 (bus, oneOut[1], zeroOut[1], clk, ~init,
		         oneOut[0], zeroOut[0]);   
   oddSlice  rung2 (bus, oneOut[2], zeroOut[2], clk, ~init,
		         oneOut[1], zeroOut[1]);
   evenSlice rung3 (bus, oneOut[3], zeroOut[3], clk, ~init,
		         oneOut[2], zeroOut[2]);
   oddSlice  rung4 (bus, oneOut[4], zeroOut[4], clk, ~init,
		         oneOut[3], zeroOut[3]);

   assign from_peg = bus[3:2];
   assign to_peg   = bus[1:0];
   assign done     = oneOut[4];

endmodule /* tower */


/****************************************************************************\
 *                                                                          *
 *  The final stimulus module is used to check that the tower module works  *
 *  properly                                                                *
 *                                                                          *
\****************************************************************************/

module stimulus;

   /*
    *  This is a behavioural model.  It simply instantiates the tower
    *  module, provides it with inputs and monitors its outputs.
    */

   reg	      clk, button;
   wire [1:0] from, to;
   wire	      done;
   
   tower t_0(from, to, done, clk, button);
   
   initial begin
      clk = 0;
      forever #(`clk_period / 2) clk = ~clk;
   end
   
   initial begin
      button = 0;      
      #40 button = 1;
      #50 button = 0;
   end

   always @(posedge clk)
      #(`clk_period - 1) $display($time, "  From peg %d To peg %d", 
				  from, to);

   always @(posedge clk)
      if (done == 1) #`clk_period $stop;
   
endmodule /* stimulus */
	   
    

Negative Edge Triggering