VHDL based design

Entering a VHDL-based Design

An alternative way to using the Schematic or the ABEL editor is to enter a VHDL/Verilog-based design . In this section you will learn how to enter a VHDL-based design using the HDL-flow mode. If you are not familiar with VHDL, consult the VHDL Reference Guide (on the Xilinx web site) or a textbook on VHDL. Figure 1 shows schematically the different steps involved in the creation of a HDL-based project.

Figure 1: Overview of the design and implementation sequence of a HDL Flow project.

In this tutorial you will learn how to enter and synthesize a VHDL based design. Once you have synthesized the VHDL file, the remaining steps of implementation and downloading will be identical as the ones for the Schematic Flow mode.

i. Open a Project in the Foundation Project Manager

If you are not in the Foundation Project Manager, open it now and create a new project called EasyVHDL. We will create the same logic function as was done before in the Schematic Entry section (circuit of Figure 2). Go to the FILE -> NEW PROJECT menu. In the pop up window, select for flow "HDL". The family and part pull down menus will not be displayed, since you will specify this later during the synthesis process (Figure 1 above).

Figure 2: Logic circuit to be implemented as a VHDL file.

ii. Create a VHDL Design and assign port names with the HDL Wizard

In the Foundation Project Manager, click on the HDL Editor icon or go to the TOOLS -> DESIGN ENTRY ->HDL EDITOR menu. Select HDL Design Wizard. In the Design Wizard window click NEXT and go to the Design Wizard Language window. Select VHDL as the design language. Click on NEXT button which will open the Design Wizard Name window. Enter the name of your design. Lets call it EasyVHDL. You can give it another name, but the name should not be larger than 8 characters.

Then click NEXT. The Design Wizard Ports window will appear showing a symbol on the left. Follow the instructions in this window. You can create here the input and output pins (ports). Use the same names as you did for the schematic of Figure 2 (DOOR, IGNITION, SBELT and BUZZER). Click on the NEW button and enter the Name, select as Direction Input or Output, depending on the type of port. For output pins you go to the ADVANCED button which will open the Advanced Port Setting windows. Select STD_LOGIC. When done, click on the FINISH button. The HDL Editor window will open at this point.

iii. Create the Source with the VHDL Editor

The HDL editor window will open a template which contains the Entity and Architecture section. The Entity section contains the input and output Port declarations made in the previous step. You should verify that all the inputs and outputs are present. The Architecture section contains the logic description of the circuit. Logic descriptions can be entered in a variety of ways: Equations, Truth Tables, and State Description (for sequential circuits). We will be using an equation to define the logic function of Figure 2. Under the Architecture section (<<enter your statements here>> ) type the following equation:

   BUZZER <= IGNITION and (not DOOR or not SBELT);

Figure 3 gives the VHDL source file for the circuit of Figure 2.

Figure 3: VHDL Editor window for the circuit if Figure 1 (Screen clip from Xilinx (TM) Foundation software)

To find out more about the VHDL syntax click on the Language Assistant icon on the top right the toolbar, or select TOOLS -> LANGUAGE ASSISTANT. This will bring up a window with language and synthesis templates. The language templates shows basic language constructs while the synthesis templates give the code of functional blocks such as counters, multiplexers, adders, flip-flops and architectures features such as Boundary Scan and RAM blocks. Figure 4 shows the Language Assistant window.

Figure 4: VHDL Language Assistant window showing the template for a multiplexer. (Screen clip from Xilinx (TM) Foundation software)

iv. Check Syntax

Lets make sure no syntax errors have been made. Go to the SYNTHESIS -> CHECK SYNTAX menu. If successful, a pop-up window will show "Check Successful". Also, the bottom window pane in the Project Manager will display a status of the process or report any errors. To learn more about the errors, open the synthesis report (SYNTHESIS -> VIEW REPORT in the HDL Editor window).

v. Add the design to the Project

To make the HDL source file part of the Project go to the PROJECT -> ADD TO PROJECT menu in the HDL Editor window. The easyvhdl.vhd file should now appear in the Project Directory on the Project Manager Window (Files tab). You can now exit the HDL editor. You will notice that the right window pane in the Project Manager shows an additional icon for the Synthesis operation (Figure 5). In case you want to create a macro, select PROJECT -> CREATE MACRO (see section on Macros and Hierarchical designs)

Figure 5: Project Manager for the HDL flow mode. (Screen clip from Xilinx (TM) Foundation software)

vi. Analyzing and Synthesizing the Design

First you will analyze the syntax by going to SYNTHESIS -> ANALYZE ALL SOURCES menu in the Project Manager window. To view warnings or errors click on the HDL Errors, Warnings of Messages Tab at the bottom of the Project Manager. When the files have been successfully analyzed you can translate the design into gates, optimized for the target device.

You can check the Synthesis Options and change the default settings if needed, by going to the SYNTHESIS -> OPTIONS menu in the Project Manager window. Click OK when done. If it ask you to re-analyze all sources, go to the SYNTHESIS -> FORCE ANALYSIS of ALL SOURCES menu.
Click on the Synthesis icon in the Project Manager window (Flow tab). This will open the Synthesis/Implementation settings window, shown below. You can now specify the top level module (in the HDL mode you specify the top-level module during the synthesis operation in contrast to the Schematic flow mode when you specify the top level module when you create your project). In our case we only have one module, called EasyVhdl. However, for more a complicated design you need to specify what the top level design is. The processing will then start from this module and progress through all the underlying designs. Fill out the version name, select the target family and device. If you check "Edit Synthesis/Implementation constraints", you will be able to enter constraints for your design using the Express Constraint Editor. When you "View Estimated Performance after Optimization" you can view the estimated performance results.

Figure 6: Synthesis Settings/Implementation window. (Screen clip from Xilinx (TM) Foundation software)

Click on the SET button. In the Setting window you can ask to optimize the synthesis for Area or Speed. You can also specify the target clock frequency. Select Insert I/O pads. This will add input and output pads to the top-level module. When done, click OK.

Figure 7: Synthesis settings window. (Screen clip from Xilinx (TM) Foundation software)

Click RUN to start the synthesis of the design.

You can now proceed with a functional simulation by clicking on the Simulation Icon in the Project Manager. Alternatively, you can implement your design.

References:

"Foundation Series 2.1i User Guide , Chapter 5, Design Methodologies - HDL Flow", available on the Xilinx website.
D. Van den Bout, "The Practical Xilinx Designers Lab Book 1.5", Prentice Hall, Upper Saddle River, 1999.
J. Wakerly, "Digital Design", 2nd Edition, Prentice Hall, Upper Saddle River, 2000.
VHDL Reference Guide, Foundation online help, Xilinx web site.

Created by Jan Van der Spiegel; August 26, 1997; Updated by Jan Van der Spiegel May 16, 2000.
<jan@ee.upenn.edu>;